Cpu Interrupt Assignment - Digital Equipment AlphaPC64 User Manual

The AlphaPC64 interrupt controller has 17 interrupts: four from each of the
four PCI slots (16) and one from the SIO bridge.
All PCI interrupts are combined in the PLD and drive a single output signal,
pci_isa_irq. This signal drives CPU input cpu_irq0 through a multiplexer.
There is also a memory controller error interrupt and an I/O controller error
interrupt within the CPU.
Table 4–1 lists the CPU interrupt assignment during normal operation.
Table 4–1 CPU Interrupt Assignment
Interrupt CPU
Source Interrupt
pci_isa_irq cpu_irq0
rtc_irq_l cpu_irq1
nmi cpu_irq2
— cpu_irq3,
cpu_irq4
sys_irq0 cpu_irq5
Three jumpers (J3-3, J3-5, and J3-7) connect to one side of the multiplexer.
The jumper configuration sets the CPU clock multiplier value through the
cpu_irqn inputs during reset.
4.1 PCI Interrupts and Arbitration
Description
Combined output of the interrupt PLD
Real-time clock interrupt from DS1287
Nonmaskable interrupt from the SIO bridge
Not used; tied to ground
Hardware interrupt from the PCI host bridge
(21071-CA)
Functional Elements 4–3