Cobra MR HH325VP Service Manual page 5

switching circuit to receive. The received RF signal is sent to a SAW filter F1 to filter out-of-band signal.
The RF amplifier Q7 amplifies signals within the range of the frequency coverage and passes though
another saw filter F2 to further filter out-of-band signals. The RF signal then is mixed with the local
oscillation frequency by the mixer Q8. A first IF (Intermediate Frequency) 21.4 MHz is produced. The IF
is passed through a pair of crystal filter F3 (1/2), F4 (2/2) to further filter other unwanted signal. The first
IF then is amplified by Q2 and the IF amplifier U1 (BA4116). U1 is a integrated RF amplifier which
consists of a local oscillator, a demodulator, a second mixer, squelch control circuit, and RF amplifier.
The 21.4 MHz IF then is mixed here with second mixer and converted into 2nd IF 450 kHz. The 2nd IF
passes through a ceramic filter F5 to filter out the residue unwanted signal at pin 5 of U1 (BA4116) output
this final IF signal and the audio signal is output at pin 9 of U1 (BA4116).
The audio signal is fed through a volume control VR3 and finally amplified by audio amplifier U11
(NJM2070) and heard in the speaker.
The squelch control is also controlled by U1 (BA4116). The second IF passes through U1 (BA4116)
internal squelch control R90, C141, C142 form as a squelch amplifier. The ceramic filter produces a
squelch signal (RF noise). Pin 14 of U1 sends the digital squelch control signal to the CPU mute the audio
speaker path. Pin 12 of U1 output a RSSI level to the CPU.
Low Voltage Detection
The battery voltage, divided by R148, R149 is input to U7 Pin 6 for voltage level sample.
Vibration Alert
When vibration alert is necessary, U7 Pin 54 outputs HI level to turn ON M1 vibration Motor through Q23.
PLL (Phase Lock Loop) Circuit
The receiver and transmitter both share the same PLL (Phase Lock Loop) Circuit to produce the carrier or
the receive frequency. The local oscillator consists of a fundamental frequency oscillator X2 20.95MHz,
PLL U6 (KB8825), TX VCO Q14 and RX VCO Q13. The fundamental frequency is frequency divided by
U6 and a 12.5 KHz signal is produced. When the VCO frequency applied to and frequency divided by U6
produces a frequency comparable to 12.5 KHz, PLL will control the VCO. When these two frequencies
are matched, a constant control voltage is output from PLL to lock VCO in desired frequency. The PLL
also will output a lock indication to U7 MCU to indicate the PLL is in frequency lock state.
Memory Backup
U9 AT24C16 is an EEPROM which acts as a memory backup for the working status. When the unit is
switched ON, the MCU will reset the system, clear the RAM, and recall in the memory from the EEPROM
U9 to refresh the RAM in CPU U7.
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