Initiating An Ultra Dma Data In Burst - Maxtor 33073H4 Manual

Ultra DMA Timing
TIMING PARAMETERS (all times in nanoseconds)
t
Cycle Time (from STROBE edge to STROBE edge)
CYC
t2 Two cycle time (from rising edge to next rising edge or
CYC
from falling edge to next falling edge of STROBE)
t
Data setup time (at recipient)
D S
t
Data hold time (at recipient)
DH
t Data valid setup time at sender (time from data bus being
DVS
valid until STROBE edge)
t Data valid hold time at sender (time from STROBE edge
DVH
until data may go invalid)
t
First STROBE (time for device to send first STROBE)
F S
t Limited interlock time (time allowed between an action by
L I
one agent, either host or device, and the following action
by the other agent)
t Interlock time with minimum
MLI
t
Unlimited interlock time
U I
t
Maximum time allowed for outputs to release
A Z
t
Minimum delay time required for output drivers turning on
ZAH
(from released state)
t
ZAD
t Envelope time (all control signal transitions are within the
ENV
DMACK envelope by this much time)
t STROBE to DMARDY (response time to ensure the
S R
synchronous pause case when the recipient is pausing)
t Ready-to-final-STROBE time (no more STROBE edges
RFS
may be sent this long after receiving DMARDY- negation)
t Ready-to-pause time (time until a recipient may assume
R P
that the sender has paused after negation of DMARDY-)
t
Pull-up time before allowing IORDY to be released
IORDYZ
t Minimum time device shall wait before driving IORDY
Z I O R D Y
t Setup and hold times before assertion and negation of
ACK
DMACK-
t Time from STROBE edge to STOP assertion when the
S S
sender is stopping
DMARQ
(device)
DMACK-
(host)
STOP
(host)
HDMARDY-
(host)
DSTROBE
(device)
DD(15:0)
DA0, DA1, DA2,
CS0-, CS1-
MODE 0
MIN MAX
112
230
15
5
70
6
0 230
0 150
20
0
10
20
0
20 70
50
75
160
20
0
20
50
t
UI
t t
ACK ENV
t
ZAD
t t
ACK ENV
t
ZAD
t
ZIORDY
t
AZ
t
ACK
Figure 5 - 4

Initiating an Ultra DMA Data In Burst

MODE 1 MODE 2 MODE 3
MIN MAX MIN MAX MIN
73 54 39
154 115 86
10 7 7
5 5 5
48 30 20
6 6 6
0 200 0 170 0
0 150 0 150 0
20 20 20
0 0 0
10 10
20 20 20
0 0 0
20 70 20 70 20
30 20
70 60
125 100 100
20 20
0 0 0
20 20 20
50 50 50
t
FS
t
FS
t t
VDS DVH
AT INTERFACE DESCRIPTION
MODE 4
MAX MIN MAX
25
57
5
5
6
6
130 0 120
100 0 100
20
0
10 10
20
0
55 20 55
NA NA
60 60
100
20 20
0
20
50
5 – 5