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4.0 FUNCTIONAL DIAGRAM
+3.3
PIN
GND
PAGE 3
PAGE 4
Clock Network
Manager II
4 LVCMOS Ports
2.5V
1.5V Linear
Regulator
Regulator
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3.3V
3.3V
PAGE 5
BNC
2.5V
Figure 1. Notional UT200SpW4RTR-EVB block diagram
PAGE 2
4 TX_CLK_IN
HOST CLK
UT200SpW4RTR
SpaceWire Router
Xilinx V2
JTAG
+3.3V
+5.0V
Gaisler Board J9 Connector
BNC
BNC
3.3V
5.0V
2
4 LVDS SpW
Xilinx
PROM
JTAG
PAGE 1
PAGE 6
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