Download
Share
Print this page
  1. Manuals
  2. Brands
  3. Aeroflex Manuals
  4. Network Router
  5. UT200SpW4RTR-EVB
  6. User manual

Aeroflex UT200SpW4RTR-EVB User Manual

4-port spacewire router evaluation board
Hide thumbs

Advertisement

Quick Links

Download this manual
Standard Products
UT200SpW4RTR-EVB 4-Port SpaceWire
Router Evaluation Board Users Guide
User Manual
November, 2010
www.aeroflex.com/spacewire
1.0 INTRODUCTION
The UT200SpW4RTR-EVB is a 4-Port SpaceWire Router evaluation board designed to allow the system designer access to all
the features of the UT200SpW4RTR 4-Port router as defined in the datasheet (www.aeroflex.com/spacewire). The 4-Port
router is capable of operating at data rates from 10 to 200 Mbps. A parallel host interface is accessible through an onboard
FPGA. The Evaluation board can also be plugged into the Aeroflex Gaisler LEON 3-FT evaluation board, further expanding
functionality of the UT200SpW4RTR-EVB.
The UT200SpW4RTR router implements a non-blocking crosspoint switch and a "Round Robin" arbitration scheme allowing
all five receive ports access to all five transmit ports. Path and logical addressing are supported (Per ECSS-E-ST-50- 12C) and
lookup table storage is replicated five times giving each receive port a dedicated block of memory for logical addressing.
Configuration of lookup tables, as well as, access to internal registers may occur through any of the five ports using a simple
configuration protocol. A group adaptive function is also provided for two ports when implementing logical addressing.
Each of the four SpaceWire ports is capable of running at an independent speed. The clocking of the 4-port router is provided
by Aeroflex's Clock Network Manager II. This allows the users systems to be configured with nodes/instruments running at
different speeds.
2.0 SCOPE
This document describes the features and necessary steps to set-up and operate the Aeroflex SpaceWire 4-port Router
Evaluation Board. It is recommended that the user be familiar with the UT200SpW4RTR 4-Port SpaceWire Router datasheet.
3.0 REFERENCE DOCUMENTS
ESA Publications Division, "SpaceWire Standard: ECSS-E-ST-50-12C",
Aeroflex, "UT200SpW4RTR Datasheet",
Aeroflex, "UT7R2XLR816 Datasheet",
Aeroflex, "UT54LVDS031LV Datasheet",
Aeroflex, "UT54LVDS032LV Datasheet",
Aeroflex Gaisler GR-CPCI-UT699 LEON3-FT CPCI Development Board,
www.aeroflex.com
www.aeroflex.com
www.aeroflex.com
www.aeroflex.com
1
http://www.ecss.nl/.
www.gaisler.com

Advertisement

loading

Summary of Contents for Aeroflex UT200SpW4RTR-EVB

  • Page 1 1.0 INTRODUCTION The UT200SpW4RTR-EVB is a 4-Port SpaceWire Router evaluation board designed to allow the system designer access to all the features of the UT200SpW4RTR 4-Port router as defined in the datasheet (www.aeroflex.com/spacewire). The 4-Port router is capable of operating at data rates from 10 to 200 Mbps. A parallel host interface is accessible through an onboard FPGA.

  • Page 2: Functional Diagram

    Xilinx Xilinx V2 PROM 2.5V 1.5V Linear JTAG Regulator Regulator JTAG PAGE 1 Powered from Powered from 3.3V 3.3V +3.3V +5.0V Gaisler Board J9 Connector PAGE 4 PAGE 6 PAGE 5 2.5V 3.3V 5.0V Figure 1. Notional UT200SpW4RTR-EVB block diagram...
  • Page 3 5.0 FEATURES AND GENERAL OPERATION The Aeroflex 4-Port SpaceWire Router evaluation board is designed to provide the user a flexible means to configure, control, access, and route data through the UT200SpW4RTR device. Power to the board may be provided through the J9 connector on the GR-UT699 CPCI Development Board or through the BNC connectors.
  • Page 4 5.1.1 External Power Power to the UT200SpW4RTR-EVB may be provided externally using the three BNC connectors. 5.0V, 3.3V and 2.5V must be provided to the board. In order to use external power provided by the BNC connectors the user must jumper J57, J58, and J59. These jumpers ensure that external power is flowing to the board.
  • Page 5 Aeroflex Gaisler Board Power Power to the UT200SpW4RTR-EVB may also be provided from the J9 connector on the GR-CPCI-UT699 LEON3- FT CPCI Development Board. Jumpers J64 and J65 must be set in order for the 120 pin J63 connector on the 4-Port EVB to receive power from the LEON-3FT board.
  • Page 6 5.2 UT200SpW4RTR 4-Port Router The 4-Port router can be easily configured using any of the four SpaceWire ports or the Host port connected to the V2. If the user is going to use the XC18V04VQ44 Xilinx PROM (44-VTQFP) with the Virtex 2 - XC2V500 (FG256/FGG256) jumpers should be added to J6, J9, and J10 for proper access from the PROM to the FPGA.
  • Page 7 5.2.4 /RST Control Signal The /RST pin is connected to push button switch SW1. /RST is active low. If the router needs to be reset the user can push this switch and the router resets. After the router is reset the user should ensure that all the configuration and status register are properly set to the desired configuration.
  • Page 8 5.2.5 HOST Port Interface Access to the 5 port of the HOST port of the UT200SpW4RTR can be accomplished by writing code targeted to the Virtex 2 FPGA. Signals used to access the HOST port are listed below. Access to the HOST port can only be achieved by using the V2.
  • Page 9 Table 3. LEON-3FT Evaluation Board Connector (J9) to V2 Connection Table Virtex 2 - XC2V500 (FG256/FGG256) LEON-3FT Evaluation Board (J9) Signal Description Signal Name IO_L05N_5/VRP_5 IO_L93P_7/VREF_7 IO_L93N_7 IO_L94P_7 IO_L94N_7 IO_L96P_7 IO_L96N_7 IO_L94N_3 IO_L05P_5/VRN_5 IO_L94P_3 IO_L04N_5 IO_L43N_3 IO_L04P_5/VREF_5 IO_L45P_3 IO_L03N_5/D4/ALT_VRP_5 IO_L45N_3/VREF_3 IO_L03P_5/D5/ALT_VRN_5 IO_L06P_3 IO_L02N_5/D6...
  • Page 10 IO_L91N_3 OEN (LEON-3FT) IO_L93N_3/VREF_3 WRITEN (LEON-3FT) IO_L93P_5 RAMOEN0 IO_L93N_5 RAMOEN1 IO_L92P_5 RAMSN0 IO_L92N_5 RAMSN1 5.2.7 SpaceWire Interfaces 5.2.7.1 LVDS Interface The LVDS SpaceWire ports on the UT200SpW4RTR are connected to SpaceWire connectors located closest to the Router device. Table 4. LVDS SpaceWire to UT200SpW4RTR port connection table SpaceWire Port (LVDS) Connector Termination resistors are present on the receive signals of the LVDS SpW ports.
  • Page 11 Table 7. LVDS Receiver UT54LVDS032LV Enable Configuration Enable Signal Input Output RIN+ - RIN- ROUT All other combinations VID≥0.1V of ENABLE signals VID≥-0.1V Fail Safe Mode Table 8. Switch 2 LVDS Devices Connection Table Switch 2 (SW2) Position Name Port Enabled TX 1 ENABLE (EN) 1 and 2 TX 1 ENABLEB (/EN)
  • Page 12 5.2.9.1 Manual Jumper Control (43 Pin header) Control of the CNM can be accomplished using the corresponding pin on the 43 pin connector to set the proper configuration as reported by the UT7R2XLR816 Clock Network Manager Software GUI. The row of pins on the left or on the inside of the board are connected to 3.3V. The pins towards the outside of the board are connected to VSS and the center row is connected to the pin of the CNM.
  • Page 13 5.2.9.2 V2 Control The CNN device can also be controlled using the on board Virtex-2 device. Control of the CNM can be achieved by writing code for the V2 device that address the signals listed in the following table. Table 11. UT7R2XLR816 CMN to V2 connection table Virtex 2 - XC2V500 (FG256/FGG256) UT7R2XLR816 - 168 LGA Signal Description...
  • Page 14 5.2.9.3 Initialization Divide Registers All SpaceWire ports follow the initialization procedure as defined in ECSS-E-ST-50-12C. Following are the key components of the initialization process. After a reset or disconnect the link initiates operation at a signaling rate of 10 Mbps, ±1 Mbps. This provides the system with a common data rate while the system is checked for proper operation.
  • Page 15 UT54LVDS031LV Figure 5. TX_DIV[4:0] Jumper Locations 5.2.9.3.2 V2 Control The Initialization Divide Registers can also be controlled using the on board Virtex-2 device. Control of the TX_DIV[4:0] pins can be achieved by writing code for the V2 device that address the signals listed in the following table. Table 13.
  • Page 16 5.2.9.4 Clock Network Manager Configuration Each of the Divide Select banks contain output division selector and controller pins. There are four ternary inputs used to control the 0Q[1:0], 1Q[1:0], 2Q[1:0], 3Q[1:0], 5Q[1:0], 7Q[1:0], and FB_DS[1:0] output clock dividers, inverters, and enable controls. See Table 1 in the UT7R2XLR816 Clock Network Manager Datasheet for output behavior resulting from each combination of these pins.
  • Page 17 Table 17. The Signal Highlighted in blue is the Signal Used to Clock TXCLK_IN_4 PIN# CNM NAME 3Q_DS3 3Q_DS2 3Q_DS1 3Q_DS0 3Q_PS1 3Q_PS0 Table 18. The Signal Highlighted in blue is the Signal Used to Clock HOST_CLK and the purple Highlighted Signal is Used to Clock the V2 PIN# CNM NAME...
  • Page 18 Click [Configure] button Bank 0 200 Bank 1 200 Bank 2 100 Bank 3 100 Bank 4 50 (HOST_CLK must be set to 0.25 times the fastest TXCLK_IN) Bank 5 Don’t Care Bank 6 Don’t Care Bank 7 Don’t Care Click [Calculate Configuration] Select the configuration that best meets the systems needs.
  • Page 19 Figure 7. Configuration Schematic This is the configuration schematic that will be used to configure the Clock Network Manager for the clocking of the UT200SpW4RTR and the V2 FPGA.
  • Page 20 Table 20. Details the header pin configuration for the example of how to configure the CMN VSS = connect the center pin to the VSS pin next to it VDD = connect the center pin to the DD pin next to it NC = Do not connect the center pin to anything Header Pin CNM Pin...
  • Page 21 Figure 8. Example CNM Jumper Setting...

  • Page 22: Configuration Ports

    5.2.9 Router Configuration Protocol The user may want to access to the configuration and status registers. Access to these registers can be accomplished though any one of the four SpaceWire ports or the External Port. The default configuration is for all ports to be configuration ports.
  • Page 23 Figure 10. Configuration Read Command 5.2.9.9 Configuration Read Response A read response will be sent back to the requesting address after a Read command is executed. The Read packet command as shown in Figure 5 sets, up the address to read data from (Address LSB/MSB) and how many 8-bit values to read (Count), and the return address bytes path.
  • Page 24 • Use Write configuration protocol into port 5 of the router • Address Bytes: NONE Needed • 0x00 for configuration • Router ID: 00 for router (default) • Protocol ID: 00 for no protocol used • Packet Type: 00 is Write •...

  • Page 25: Port Addressing

    6.0 PORT ADDRESSING 6.1 Path Addressing Path Addressing is defined as a series of one or more characters at the start of the packet that define the route, or path, that the packet should take across a SpaceWire network. The destination address is specified as a sequence of router output port numbers used to route the packet across the network.
  • Page 26 6.5.2 Group Adaptive Address Bits Bits [9:5] are used when Group Adaptive has been enabled and the port selected by the Primary Logical Address Bits is busy. If group adaptive routing is not enabled and port selected by the Primary Logical Address Bits is busy, the packet waits until the selected port is free.
  • Page 27 • Write directly into port 5 of the Router, no Address Bytes required • 0x00 for configuration • Router ID: 00 for router ID (default) • Protocol ID: 00 for no protocol used • Packet Type: 00 is Write • Set up look-up table Address LSB: 20 sets up first address in look up table Address MSB: 00 the address MSB is always 00 because the address range of the Logical Addresses...
  • Page 28 6.5.8 Look up table configuration Example 2 Assume the user wants to confirm the configuration write just preformed on look up table address 0x0020 was completed correctly. The user can then use the read configuration command. The following example details hope to accomplish this. •...
  • Page 29 To quickly get the UT200SpW4RTR-EVB up and running the following steps should be followed 1. Connect headers J57, J59, and J58 This will enable external power supplies to be used b. Ensure that headers J64 and J65 are not connected.
  • Page 30 The UT200SpW4RTR-EVB can plug directly into the J9 connector on the LEON-3FT evaluation board. A ribbon cable can also be used to easily use the SpaceWire evaluation board with the LEON-3FT board when the LEON board is plugged into a cPCI chassis.
  • Page 31 10.0 BOARD SCHEMATICS The schematics in Appendix A are for reference ONLY.
  • Page 32 Change Block Redesigned board for customer use Board can plug into Aeroflex/Gaisler LEON-3FT Evaluation Board or be used as a table top board UT200SpW4RTR-CUSTOMER-EVB Schematic NOTICE TO ALL PERSONS RECEIVING THIS DRAWING: THIS DOCUMENT IS PROPERTY OF AEROFLEX COLORADO SPRINGS AND IS DELEVERED ON THE EXPRESS CONDITION THAT IT IS NOT TO BE Aeroflex Colorado Springs Aeroflex Colorado Springs...
  • Page 33 Colorado Springs Colorado Springs Colorado Springs NC15 NC16 Colorado 80907 Colorado 80907 Colorado 80907 XC18V04VQ44 XC18V04VQ44 UT200SpW4RTR-EVB FPGA - V2 UT200SpW4RTR-EVB FPGA - V2 UT200SpW4RTR-EVB FPGA - V2 Size Size Size CAGE Code CAGE Code CAGE Code DWG NO DWG NO...
  • Page 34 4350 Centennial Blvd. TX2_S+ Colorado Springs Colorado Springs Colorado Springs Colorado 80907 Colorado 80907 Colorado 80907 RX2_S- RX2_S+ RX2_D- RX2_D+ UT200SpW4RTR-EVB Router UT200SpW4RTR-EVB Router UT200SpW4RTR-EVB Router Size Size Size CAGE Code CAGE Code CAGE Code DWG NO DWG NO DWG NO...
  • Page 35 4350 Centennial Blvd. 4350 Centennial Blvd. 4350 Centennial Blvd. Colorado Springs Colorado Springs Colorado Springs Colorado 80907 Colorado 80907 Colorado 80907 UT200SpW4RTR-EVB CLK Management UT200SpW4RTR-EVB CLK Management UT200SpW4RTR-EVB CLK Management Size Size Size CAGE Code CAGE Code CAGE Code DWG NO...
  • Page 36 Aeroflex Colorado Springs 4350 Centennial Blvd. 4350 Centennial Blvd. 4350 Centennial Blvd. Colorado Springs Colorado Springs Colorado Springs Colorado 80907 Colorado 80907 Colorado 80907 UT200SpW4RTR-EVB LVDS UT200SpW4RTR-EVB LVDS UT200SpW4RTR-EVB LVDS Size Size Size CAGE Code CAGE Code CAGE Code DWG NO...
  • Page 37 Aeroflex Colorado Springs 4350 Centennial Blvd. 4350 Centennial Blvd. 4350 Centennial Blvd. Colorado Springs Colorado Springs Colorado Springs Colorado 80907 Colorado 80907 Colorado 80907 UT200SpW4RTR-EVB POWER UT200SpW4RTR-EVB POWER UT200SpW4RTR-EVB POWER Size Size Size CAGE Code CAGE Code CAGE Code DWG NO...
  • Page 38 Aeroflex Colorado Springs 4350 Centennial Blvd. 4350 Centennial Blvd. 4350 Centennial Blvd. Colorado Springs Colorado Springs Colorado Springs Colorado 80907 Colorado 80907 Colorado 80907 UT200SpW4RTR-EVB GAISLER UT200SpW4RTR-EVB GAISLER UT200SpW4RTR-EVB GAISLER Size Size Size CAGE Code CAGE Code CAGE Code DWG NO...

  • Page 39: Ordering Information

    ORDERING INFORMATION UT200SpW4RTR-EVB: UT ***** Device Type: 200SpW4RTR-EVB = 4-port SpaceWire Evaluation Board...
  • Page 40 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi – Rel...