Circuit Description - Samsung SGH-X620 Service Manual

2. Circuit Description

2-1. SGH-X620 RF Circuit Description
2-1-1. RX PART
- ASM(U100) ¡ æ
Switching Tx, Rx path for GSM900, DCS1800, PCS1900 by logic controlling.
- ASM Control Logic (U100) ¡ æ
Tx Mode (GSM900)
Tx Mode (DCS1800/1900)
Rx Mode (GSM900)
Rx Mode (DCS1800)
Rx Mode (PCS1900)
- VC-TCXO (OSC101)
This module generates the 26MHz reference clock to drive the logic and RF. After division by two a reference clock of
13MHz is supplied to the other parts of the system through the pin CLKOUT. After additional process, the reference
clock applies to the U100 Rx IQ demodulator and Tx IQ modulator. And then, the oscillator is controlled by serial data
to select channel and use fast lock mode for GPRS high class operation.
- Transceiver (U101)
The receiver front-end which amplifies the GSM, DCS aerial signal, converts the chosen channel down to a low IF signal
of 100 kHz. The first stages are symmetrical low noise amplifiers (LNAs). The LNAs are followed by an IQ down mixer.
It consists of two mixers in parallel but driven by quadrature out of phase LO signals. The In phase (I) and Quadrature
phase (Q) IF signals are low pass filtered to provide protection from high frequency offset interferes. The low IF I and Q
signals are then fed into the channel filter. The front-end low IF I and Q outputs enter the integrated bandpass channel
filter with provision for five 8 dB gain steps in front of the filter.
2-1-2. TX PART
I and Q baseband signals are applied to the IQ modulator that shifts the modulation spectrum up to the transmit IF. It is
designed for low harmonic distortion, low carrier leakage and high image rejection to keep the phase error as small as
possible.
The modulator is loaded at its IF output by an integrated low pass filter that suppress unwanted spurs prior to get into
the phase detector. The clock drive is generated by division of the RFLO signal provided for the transmit offset mixer.
Baseband IQ signal fed into offset PLL, this function is included inside of U101 chip. OSC100 chip generates modulator
signal which power level is about 6.5dBm and fed into Power Amplifier(U102). The PA output power and power ramping
are well controlled by Auto Power Control circuit. We use offset PLL below table.
Truth Table
VC1
H
L
L
L
L
SAMSUNG Proprietary-Contents may change without notice
This Document can not be used with out Samsung' s authorization
VC2
L
H
L
L
L
2- 1
VC3
L
L
L
L
H