Samsung SGH-E730 Service Manual page 7

Gsm telephone
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2-2-5. EMI ESD Filter
This system uses the EMI ESD filter, U500 to protect noise from IF CONNECTOR part.
2-2-6. IF connetor
It is 18-pin connector. They are designed to use VBAT, V_EXT_CHARGE, USB_D+, +VBUS, USB_D-, TXD1, RXD1,
AUX_ON, EXT1, EXT2, and GND. They connected to power supply IC, microprocessor and signal processor IC.
2-2-7. Battery Charge Management
A complete constant-current/constant-voltage linear charger for single cell lithium-ion batteries.
If TA connected to phone, "V_EXT_CHARGE" enable charger IC and supply current to battery.
When fault condition caused, "CHG_ON" signal level change low to high and charger IC stop charging process.
2-2-8. Audio
HFR_P and HFR_N from PCF5212EL1EL1 are connected to the main speaker via analog switches. MIC_P and MIC_N
are connected to the main MIC as well. EAR1 is the source of External Speaker. YMU765 is a synthesizer LSI for
mobile phones. This LSI has a built-in speaker amplifier for outputting sounds that are used by mobile phones in addition
to game sounds and ringing melodies that are replayed by a synthesizer.
The synthesizer section adopts ¡° stereophonic hybrid synthesizer system ¡± that are given advantages of both FM
synthesizers and Wave Table synthesizers to allow simultaneous generation of up to 32 FM voices and 32 Wave
Table voices.
It provides simultaneous generation of up to 64 tones by stereophonic hybrid synthesizer.
YMU765 has built a speaker amplifier of which maximum out is 580 mW at SPVDD=3.6V in this device.
There is Stereophonic analog output for Headphone.
2-2-9. Memory
This system uses Samsung's memory, KAP17WG00M-D444. The KAP17WG00M-D444 is a Multi Chip Package Memory
which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and two 1Gbit OneNAND Flash and
128Mbit Synchronous Burst UtRAM.
It has 16 bit data line, HD[0~15] which is connected to PCF5212EL1EL1 and MV3315DOQ, also has 24 bit address
lines,
HA[1~24]. There are 3 chip select signals, CS0n_FLASH, CS4n_NAND, and CS1n_RAM.
In the Wrting process, WEn is fallen to low and it enables writing process to operate. During reading process,
OEn is fallen to low and it enables reading process to operate. Each chip select signals in the PCF5212EL1EL1 choose
different memories.
2-2-10. PCF5212EL1EL1
The PCF5212EL1EL1 is mainly composed of embeded DSP and ARM core. The DSP subsystem includes the Saturn
DSP core with embedded RAM and ROM, and a set of peripherals. It has 24kx16 bits PRAM, 104k*16 bits,
32k*16 XYRAM and 63k*16 XYROM in the DSP.
The ARM946E-S consists of an ARM9E-S processor core, 8 kbyte instruction cache and 8 kbyte data cache,
tghtly-coupled ITCM(Instruction Tightly Coupled Memory) and DTCM(Data Tightly Coupled Memory) memories, a
memory protection unit, and an AMBA(Advanced Microcontroller Bus Architecture) AHB(Advanced
High-performance Bus) bus interface with a write buffer.
SAMSUNG Proprietary-Contents may change without notice
This Document can not be used without Samsung's authorization
2- 3
Circuit Description

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