Fairchild SEMICONDUCTOR AN-7502 Application Note

The examination of power MOSFET voltage and current
waveforms during switching transitions reveals that the
device characterization now practiced by industry is inade-
/Title
quate. In this Note, device waveforms are explained by con-
sidering the interaction of a vertical JFET driven in cascode
AN75
from a lateral MOSFET in combination with the interelec-
2)
trode capacitances. Particular attention is given to the
Sub-
drain-voltage waveform and its dual-slope nature. The
ect
three terminal capacitances now published by the industry
are shown to be valid only for zero drain current. For cases
Power
where the gate drive is a voltage step generator with inter-
OS-
nal fixed resistance, the drain voltage characteristics are
ET
inferred from the gate current drive behavior and compared
witch
to observed waveforms. The nature of the "asymmetric
switching times" is explained.
ng
ave-
A waveform family is proposed as a more descriptive and
accurate method of characterization. This new format is a
orms:
plot of drain voltage and gate voltage versus normalized
New
time. A family of curves is presented for a constant load
nsi
resistance with V
transitions is a constant current with voltage compliance
ht)
limits of 0 and 10 volts. Time is normalized by the value of
Autho
gate driving current. The normalization shows excellent
()
agreement with data over five orders of magnitude, and is
Key-
bounded on one extreme by gate propagation effects and
on the other by transition time self-heating (typically tens of
ords
nanoseconds to hundreds of microseconds).
Inter-
il
Device Models
orpo-
The keystone of an understanding of power MOSFET
ation,
switching performance is the realization that the active
emi-
device is bimodal and must be described using a model that
on-
accounts for the dual nature. Buried in today's power MOS-
FET devices is the equivalent of a depletion layer JFET that
uctor)
contributes significantly to switching speed. Figure 1 is a
Cre-
cross-sectional view of a typical power MOSFET, with MOS-
tor ()
FET/JFET symbols superimposed on the structure.
DOCI
Figure 2 is obtained by taking the lateral MOS and vertical
FO
JFET from this conception and adding all the possible node-
df-
to-node capacitances. Computed values of the six capaci-
tances for a typical device structure suggest that device
ark
behavior may be adequately modeled using only three
capacitors in the manner of Figure 3. This is the model to be
employed for analysis and study.
Page-
ode
Use-
ut-
ines
©2002 Fairchild Semiconductor Corporation
Application Note
varied. Gate drive during switching
DS
Power MOSFET Switching Waveforms:
n+ SOURCE
p BODY
p+
FIGURE 1. CROSS-SECTION VIEW OF MOSFET SHOWING
GATE
FIGURE 2. MOS TRANSISTOR WITH CASCODE-CONNECTED
GATE
Gate Drive: Constant Voltage or
Constant Current
Before moving on to the study of the equivalent circuit states
of the model, a gate-drive forcing function which is easy to
represent, relates to reality, and best illustrates device
behavior must be chosen. The choice may be immediately
narrowed to two:
(1) An instantaneous step voltage with internal resistance R,
Figure 5.
(2) An instantaneous step current with infinite internal resis-
tance, Figure 6.
A New Insight
October 1999
SOURCE METAL
POLY GATE GLASS GATE OXIDE
JFET
MOS
DEPLETION EDGE
n-
n+ DRAIN
EQUIVALENT MOS TRANSISTOR AND JFET
C6
C3
C2
C4
C1
SOURCE
JFET AND ALL CAPACITORS
C
x
C
GS
SOURCE
FIGURE 3. FIGURE 2 SIMPLIFIED
Application Note 7502 Rev. A1
AN-7502
0
10 VOLTS
40 VOLTS
DRAIN
C5
DRAIN
C
DS