Maxim MAX9777 Manual page 16

Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
There are three registers that configure the MAX9777:
the MUTE register, SHDN register, and control register.
In write data mode (R/W = 0), the register address and
data byte follow the device address (Figure 7).
The MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel; bit 4
(MUTER) controls the right channel. A logic-high mutes
the respective channel; a logic-low brings the channel
out of mute.
The SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic-high
S ADDRESS
2
I C SLAVE ADDRESS.
SELECTS DEVICE.
S ADDRESS
2
I C SLAVE ADDRESS.
SELECTS DEVICE.
Figure 7. Write/Read Data Format Example
Table 3. MAX9777 MUTE Register Format
REGISTER
ADDRESS
BIT NAME VALUE
7 X Don't Care
6 X Don't Care
5 X Don't Care
0*
4 MUTER
0*
3 MUTEL
2 X Don't Care
1 X Don't Care
0 X Don't Care
*Default state.
16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Write Data Format
MUTE Register
SHDN Register
WR ACK COMMAND
7 BITS 8 BITS
REGISTER ADDRESS.
SELECTS REGISTER TO BE
WRITTEN TO.
WR ACK COMMAND
7 BITS 8 BITS
REGISTER ADDRESS.
SELECTS REGISTER
TO BE READ.
0000 0001
DESCRIPTION
—
—
—
Unmute right channel
1 Mute right channel
Unmute left channel
1 Mute left channel
—
—
—
in bit 0 of the SHDN register shuts down the device; a
logic-low turns on the device. A logic-high is required in
bits 2 to 7 to reset all registers to their default settings.
The control register (03hex) is a read/write register that
determines the device configuration. Bit 1 (IN1/IN2) con-
trols the input multiplexer, a logic-high selects input 1; a
logic-low selects input 2. Bit 2 (HPS_D) controls the
headphone sensing. A logic-low configures the device in
automatic headphone detection mode. A logic-high dis-
ables the HPS input. Bit 3 (GAINA/B) controls the gain-
select multiplexer. A logic-low selects GAINA. A logic-
high selects GAINB. GAINA/B is ignored when HPS_D =
0. Bit 4 (SPKR/HP) selects the amplifier operating mode
when HPS_D = 1. A logic-high selects speaker mode,
and a logic-low selects headphone mode.
ACK DATA ACK P
8 BITS 1
REGISTER DATA
ACK S ADDRESS WR ACK
7 BITS
2
I C SLAVE ADDRESS.
SELECTS DEVICE.
Table 4. MAX9777 SHDN Register Format
REGISTER ADDRESS
BIT NAME
7 RESET
6 RESET
5 RESET
4 RESET
3 RESET
2 RESET
1 X
0 SHDN
*Default state.
Control Register
DATA P
8 BITS 1
DATA FROM
SELECTED REGISTER
0000 0010
VALUE DESCRIPTION
0* —
1 Reset device
0* —
1 Reset device
0* —
1 Reset device
0* —
1 Reset device
0* —
1 Reset device
0* —
1 Reset device
Don't Care —
0* Normal operation
1 Shutdown