DMA Timing
TIMING PARAMETERS
t0
Cycle Time (min)
tC
DMACK to DMARQ delay
tD
DIOR-/DIOW- (min)
tE
DIOR- data access (min)
tF
DIOR- data hold (min)
tG
DIOR-/DIOW- data setup (min)
tH
DIOW- data hold (min)
tI
DMACK to DIOR-/DIOW- setup (min)
tJ
DIOR-/DIOW- to DMACK hold (min)
tKr
DIOR- negated pulse width (min)
tKw
DIOW- negated pulse width (min)
tLr
DIOR- to DMARQ delay (max)
tLw
DIOW- to DMARQ delay (max)
tZ
DMACK- to tristate (max)
MODE 0
MODE 1
480 ns
150 ns
215 ns
80 ns
150 ns
60 ns
5 ns
5 ns
100 ns
30 ns
20 ns
15 ns
0
0
20 ns
5 ns
50 ns
50 ns
215 ns
50 ns
120 ns
40 ns
40 ns
40 ns
20 ns
25 ns
Figure 5 - 3
Multi-word DMA Data Transfer
AT INTERFACE DESCRIPTION
MODE 2
120 ns
70 ns
5 ns
20 ns
10 ns
0
5 ns
25 ns
25 ns
35 ns
35 ns
25 ns
5 – 25