Page 1 Red Hat Enterprise Linux 4 Using as, the Gnu Assembler...
Page 2 All other trademarks referenced herein are the property of their respective owners. The GPG ﬁngerprint of the security@redhat.com key is: CA 20 86 86 2B D6 9D FC 65 F6 EC C4 21 91 80 CD DB 42 A6 0E...
Page 3: Table Of Contents
Table of Contents 1. Using as ............................1 2. Overview ............................3 2.1. Structure of this Manual....................15 2.2. The GNU Assembler......................15 2.3. Object File Formats......................15 2.4. Command Line......................... 16 2.5. Input Files ........................16 2.5.1. Filenames and Line-numbers................16 2.6.
Page 4 6.5.2. Type........................37 6.5.3. Symbol Attributes: ................37 a.out 6.5.4. Symbol Attributes for COFF ................38 6.5.5. Symbol Attributes for SOM................38 7. Expressions ............................ 39 7.1. Empty Expressions......................39 7.2. Integer Expressions ......................39 7.2.1. Arguments......................39 7.2.2. Operators......................39 7.2.3.
Page 5 8.44..........................49 .ident 8.45................... 49 absolute expression 8.46................51 .incbin " "[, file skip count 8.47......................51 .include " " file 8.48......................51 .int expressions 8.49......................51 .internal names 8.50....................51 .irp symbol values...
Page 6 8.94.2. ELF Version ....................67 8.95....................67 .uleb128 expressions 8.96........................67 .val addr 8.97..................... 67 .version " " string 8.98................. 68 .vtable_entry table offset 8.99................68 .vtable_inherit child parent 8.100........................ 68 .weak names 8.101....................
Page 7 14. CRIS Dependent Features......................93 14.1. Command-line Options....................93 14.2. Instruction expansion ..................... 93 14.3. Syntax ..........................93 14.3.1. Special Characters................... 93 14.3.2. Symbols in position-independent code ............94 14.3.3. Register names ....................95 14.3.4. Assembler Directives ..................95 15. D10V Dependent Features......................97 15.1.
Page 8 19. HPPA Dependent Features....................... 117 19.1. Notes ..........................117 19.2. Options......................... 117 19.3. Syntax .......................... 117 19.4. Floating Point....................... 117 19.5. HPPA Assembler Directives ..................117 19.6. Opcodes........................121 20. ESA/390 Dependent Features ....................123 20.1. Notes ..........................123 20.2. Options......................... 123 20.3.
Page 9 26. M680x0 Dependent Features....................151 26.1. M680x0 Options ......................151 26.2. Syntax .......................... 153 26.3. Motorola Syntax......................154 26.4. Floating Point....................... 155 26.5. 680x0 Machine Directives ................... 156 26.6. Opcodes........................156 26.6.1. Branch Improvement..................156 26.6.2. Special Characters..................158 27. M68HC11 and M68HC12 Dependent Features ..............159 27.1.
Page 10 32. PDP-11 Dependent Features ....................187 32.1. Options......................... 187 32.1.1. Code Generation Options................187 32.1.2. Instruction Set Extension Options ..............187 32.1.3. CPU Model Options..................188 32.1.4. Machine Model Options ................189 32.2. Assembler Directives ....................190 32.3. PDP-11 Assembly Language Syntax ................190 32.4.
Page 11 39. Z8000 Dependent Features....................... 221 39.1. Options......................... 221 39.2. Syntax .......................... 221 39.2.1. Special Characters..................221 39.2.2. Register Names ..................... 221 39.2.3. Addressing Modes ..................221 39.3. Assembler Directives for the Z8000 ................222 39.4. Opcodes........................223 40. VAX Dependent Features ......................225 40.1.
Page 12 Index..............................261...
Page 13 Using as...
Page 15: Using As
Chapter 1. Using as This ﬁle is a user guide to the gnu assembler version 2.15.92.0.2. This document is distributed under the terms of the GNU Free Documentation License. A copy of the license is included in the section entitled "GNU Free Documentation License".
Page 16 Chapter 1. Using as...
Page 17: Overview
Chapter 2. Overview Here is a brief summary of how to invoke . For details, Chapter 3 Command-Line Options. as [-a[cdhlns][= ]] [--alternate] [-D] file [--defsym ] [-f] [-g] [--gstabs] [--gstabs+] [--gdwarf-2] [--help] [-I ] [-J] [-K] [-L] [--listing-lhs-width= ] [--listing-lhs-width2= [--listing-rhs-width= ] [--listing-cont-lines= [--keep-locals] [-o...
Page 18 Chapter 2. Overview Target M32R options: [--m32rx|--[no-]warn-explicit-parallel-conflicts| --W[n]p] Target M680X0 options: [-l] [-m68000|-m68010|-m68020|...] Target M68HC11 options: [-m68hc11|-m68hc12|-m68hcs12] [-mshort|-mlong] [-mshort-double|-mlong-double] [--force-long-branchs] [--short-branchs] [--strict-direct-mode] [--print-insn-syntax] [--print-opcodes] [--generate-example] Target MCORE options: [-jsri2bsr] [-sifilter] [-relax] [-mcpu=[210|340]] Target MIPS options: [-nocpp] [-EL] [-EB] [-O[ optimization level [-g[ ]] [-G ] [-KPIC] [-call_shared]...
Page 19 Chapter 2. Overview [-Av6|-Av7|-Av8|-Asparclet|-Asparclite -Av8plus|-Av8plusa|-Av9|-Av9a] [-xarch=v8plus|-xarch=v8plusa] [-bump] [-32|-64] Target TIC54X options: [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] [-merrors-to-file |-me filename filename ¡ ¡ Target Xtensa options: [--[no-]density] [--[no-]relax] [--[no-]generics] [--[no-]text-section-literals] [--[no-]target-align] [--[no-]longcalls] -a[cdhlmns] Turn on listings, in any of a variety of ways: omit false conditionals omit debugging directives include high-level source include assembly...
Page 20 Chapter 2. Overview -defsym value Deﬁne the symbol to be before assembling the input ﬁle. must be an integer value value constant. As in C, a leading indicates a hexadecimal value, and a leading indicates an octal value. "fast"--skip whitespace and comment preprocessing (assume source is compiler output). -gen-debug Generate debugging information for each assembler source line using whichever debug format is preferred by the target.
Page 21 Chapter 2. Overview -listing-lhs-width2= number Set the maximum width, in words, of the output data column for continuation lines in an assem- bler listing to number -listing-rhs-width= number Set the maximum width of an input source line, as displayed in a listing, to bytes.
Page 22 Chapter 2. Overview files Standard input, or source ﬁles to assemble. The following options are available when as is conﬁgured for an ARC processor. -marc[5|6|7|8] This option selects the core processor variant. -EB | -EL Select either big-endian (-EB) or little-endian (-EL) output. The following options are available when as is conﬁgured for the ARM processor family.
Page 23 Chapter 2. Overview Optimize output by parallelizing instructions. Warn when nops are generated. Warn when a nop after a 32-bit multiply instruction is generated. The following options are available when as is conﬁgured for the Intel 80960 processor. -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC Specify which variant of the 960 architecture is the target.
Page 24 Chapter 2. Overview -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at conﬁguration time.
Page 25 Chapter 2. Overview -m68hc11 | -m68hc12 | -m68hcs12 Specify what processor is the target. The default is deﬁned by the conﬁguration option when building the assembler. -mshort Specify to use the 16-bit integer ABI. -mlong Specify to use the 32-bit integer ABI. -mshort-double Specify to use the 32-bit double ABI.
Page 26 Chapter 2. Overview -bump Warn when the assembler switches to another architecture. The following options are available when as is conﬁgured for the ’c54x architecture. -mfar-mode Enable extended addressing mode. All addresses and relocations will assume extended address- ing (usually 23 bits). -mcpu= CPU_VERSION Sets the CPU version being compiled for.
Page 27 Chapter 2. Overview -mfix7000 -mno-fix7000 Cause nops to be inserted if the read of the destination register of an mfhi or mﬂo instruction occurs in the following two instructions. -mdebug -no-mdebug Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
Page 28 Chapter 2. Overview This option is currently supported only when the primary target is conﬁgured for is a mips ELF or ECOFF target. Furthermore, the primary target or others speciﬁed with at conﬁguration time must include support for the other format, if -enable-targets=...
Page 29: Structure Of This Manual
Chapter 2. Overview -relax | -no-relax Enable or disable instruction relaxation. This is enabled by default. Note: In the current imple- mentation, these options also control whether assembler optimizations are performed, making these options equivalent to -generics -no-generics -generics | -no-generics Enable or disable all assembler transformations of Xtensa instructions.
Page 30: Command Line
Chapter 2. Overview 2.3. Object File Formats The gnu assembler can be conﬁgured to produce several alternative object ﬁle formats. For the most part, this does not affect how you write assembly language programs; but directives for debugging symbols are typically different in different ﬁle formats. Section 6.5 Symbol Attributes. 2.4.
Page 31: Output (Object) File
Chapter 2. Overview is itself synthesized from other ﬁles. understands the directives emitted by the preprocessor. See also Section 8.37 .file string 2.6. Output (Object) File Every time you run it produces an output ﬁle, which is your assembly language program translated into numbers.
Page 32 Chapter 2. Overview...
Page 33: Command-Line Options
Chapter 3. Command-Line Options This chapter describes command-line options available in all versions of the gnu assembler; Chapter 9 Machine Dependent Features, for options speciﬁc to particular machine architectures. If you are invoking via the gnu C compiler, you can use the option to pass arguments through to the assembler.
Page 34: Work Faster
Chapter 3. Command-Line Options 3.3. This option has no effect whatsoever, but it is accepted to make it more likely that scripts written for other assemblers also work with 3.4. Work Faster: should only be used when assembling programs written by a (trusted) compiler. stops the assembler from doing whitespace and comment preprocessing on the input ﬁle(s) before assembling them.
Page 35 Chapter 3. Command-Line Options -listing-lhs-width2= number Sets the maximum width, in words, of any further lines of the hex byte dump for a given input source line. If this value is not speciﬁed, it defaults to being the same as the value speciﬁed for .
Page 36 Chapter 3. Command-Line Options There are some other features of the MRI assembler which are not supported by , typically either because they are difﬁcult or because they seem of little consequence. Some of these may be supported in future releases. EBCDIC strings •...
Page 37: Dependency Tracking: -Md
Chapter 3. Command-Line Options 3.10. Dependency Tracking: can generate a dependency ﬁle for the ﬁle it creates. This ﬁle consists of a single rule suitable for describing the dependencies of the main source ﬁle. make The rule is written to the ﬁle named in its argument. This feature is used in the automatic updating of makeﬁles.
Page 38: Control Warnings: -W
Chapter 3. Command-Line Options 3.16. Control Warnings: -warn -no-warn -fatal-warnings should never give a warning or error message when assembling compiler output. But programs written by people often cause to give a warning that a particular assumption was made. All such warnings are directed to the standard error ﬁle.
Page 39: Syntax
Chapter 4. Syntax This chapter describes the machine-independent syntax allowed in a source ﬁle. syntax is similar to what many other assemblers use; it is inspired by the BSD 4.2 assembler, except that does not assemble Vax bit-ﬁelds. 4.1. Preprocessing internal preprocessor: adjusts and removes extra whitespace.
Page 40: Symbols
Chapter 4. Syntax Anything from the line comment character to the next newline is considered a comment and is ignored. The line comment character is for the AMD 29K family; on the ARC; on the ARM; for the H8/300 family; for the H8/500 family;...
Page 41: Constants
Chapter 4. Syntax A label is a symbol immediately followed by a colon ( ). Whitespace before a label or after a colon is permitted, but you may not have whitespace between a label’s symbol and its colon. Section 6.1 Labels.
Page 42: Number Constants
Chapter 4. Syntax Mnemonic for carriage-Return; for ASCII this is octal code 015. Mnemonic for horizontal Tab; for ASCII this is octal code 011. digit digit digit An octal character code. The numeric code is 3 octal digits. For compatibility with other Unix systems, 8 and 9 are accepted as digits: for example, has the value 010, and the value...
Page 43 Chapter 4. Syntax 4.6.2.1. Integers A binary integer is followed by zero or more of the binary digits An octal integer is followed by zero or more of the octal digits ( 01234567 A decimal integer starts with a non-zero digit followed by zero or more digits ( 0123456789 A hexadecimal integer is followed by one or more hexadecimal digits chosen from...
Page 44 Chapter 4. Syntax...
Page 45: Sections And Relocation
Chapter 5. Sections and Relocation 5.1. Background Roughly, a section is a range of addresses, with no gaps; all data "in" those addresses is treated the same for some particular purpose. For example there may be a "read only" section. The linker reads many object ﬁles (partial programs) and combines their contents to form a runnable program.
Page 46: Linker Sections
Chapter 5. Sections and Relocation Further, most expressions computes have this section-relative nature. (For some object formats, such as SOM for the HPPA, some expressions are symbol-relative instead.) In this manual we use the notation { } to mean "offset into section ."...
Page 47: Assembler Internal Sections
Chapter 5. Sections and Relocation undeﬁned section This "section" is a catch-all for address references to objects not in the preceding sections. An idealized example of three relocatable sections follows. The example uses the traditional section names . Memory addresses are on the horizontal axis. .text .data +-----+----+--+...
Page 48: Bss Section
Chapter 5. Sections and Relocation Each subsection is zero-padded up to a multiple of four bytes. (Subsections may be padded a different amount on different ﬂavors of Subsections appear in your object ﬁle in numeric order, lowest numbered to highest. (All this to be compatible with other people’s assemblers.) The object ﬁle contains no representation of subsections;...
Page 49: Symbols
Chapter 6. Symbols Symbols are a central concept: the programmer uses symbols to name things, the linker uses symbols to link, and the debugger uses symbols to debug. Warning: does not place symbols in the object ﬁle in the same order they were declared. This may break some debuggers.
Page 50: Dollar Local Labels
Chapter 6. Symbols deﬁnition of a speciﬁc local label for a forward reference. It is also worth noting that the ﬁrst 10 local labels ( . . . ) are implemented in a slightly more efﬁcient manner than the others. Here is an example: branch 1f branch 1b...
Page 51: The Special Dot Symbol
Chapter 6. Symbols They can also be distinguished from ordinary local labels by their transformed name which uses ASCII character (control-A) as the magic character to distinguish them from ordinary labels. \001 Thus the 5th deﬁntion of is named L6C-A5 6.4.
Page 52: Symbol Attributes For Coff
Chapter 6. Symbols 6.5.3.2. Other This is an arbitrary 8-bit value. It means nothing to 6.5.4. Symbol Attributes for COFF The COFF format supports a multitude of auxiliary symbol attributes; like the primary symbol at- tributes, they are set between directives.
Page 53: Expressions
Chapter 7. Expressions An expression speciﬁes an address or numeric value. Whitespace may precede and/or follow an ex- pression. The result of an expression must be an absolute number, or else an offset into a particular section. If an expression is not absolute, and there is not enough information when sees the expression to know its section, a second pass over the source program might be necessary to interpret the expression--but the second pass is currently not implemented.
Page 54: Inﬁx Operators
Chapter 7. Expressions Complementation. Bitwise not. 7.2.4. Inﬁx Operators Inﬁx operators take two arguments, one on either side. Operators have precedence, but operations with equal precedence are performed left to right. Apart from , both arguments must be absolute, and the result is absolute.
Page 55 Chapter 7. Expressions Addition. If either argument is absolute, the result has the section of the other argument. You may not add together arguments from different sections. Subtraction. If the right argument is absolute, the result has the section of the left argument. If both arguments are in the same section, the result is absolute.
Page 56 Chapter 7. Expressions...
Page 57: Assembler Directives
Chapter 8. Assembler Directives All assembler directives have names that begin with a period ( ). The rest of the name is letters, usually in lower case. This chapter discusses directives that are available regardless of the target machine conﬁguration for the gnu assembler.
Page 58: Abs-Expr Abs-Expr
Chapter 8. Assembler Directives 8.4..ascii " " string expects zero or more string literals (Section 4.6.1.1 Strings) separated by commas. It assem- .ascii bles each string (with no automatic trailing zero byte) into consecutive addresses. 8.5. .
Page 59: Cfi_Endproc
Chapter 8. Assembler Directives The syntax for differs slightly on the HPPA. The syntax is .comm .comm, symbol symbol length is optional. 8.9. .cfi_startproc is used at the beginning of each function that should have an entry in .cfi_startproc .eh_frame It initializes some internal data structures and emits architecture dependent initial CFI instructions.
Page 60: Cfi_Window_Save
Chapter 8. Assembler Directives 8.17. .cfi_window_save SPARC register window has been saved. 8.18. [, . . . ] .cfi_escapeexpression Allows the user to add arbitrary bytes to the unwind info. One might use this to add OS-speciﬁc CFI opcodes, or generic CFI opcodes that GAS does not yet support. 8.19.
Page 61: Endfunc
Chapter 8. Assembler Directives 8.25. .else is part of the support for conditional assembly; Section 8.45 .else absolute expression It marks the beginning of a section of code to be assembled if the condition for the preceding false. 8.26. .elseif is part of the support for conditional assembly;...
Page 62: Expression
Chapter 8. Assembler Directives .equ SYM,VAL 8.33. .err assembles a directive, it will print an error message and, unless the option was used, it .err will not generate an object ﬁle. This can be used to signal error an conditionally compiled code. 8.34.
Page 63: Symbol
Chapter 8. Assembler Directives 8.39. .float flonums This directive assembles zero or more ﬂonums, separated by commas. It has the same effect as . The exact kind of ﬂoating point numbers emitted depends on how is conﬁgured. Chapter .single 9 Machine Dependent Features. 8.40.
Page 64 Chapter 8. Assembler Directives have several conditions to check, may be used to avoid nesting blocks if/else within each .elseif subsequent block. .else The following variants of are also supported: .ifdef symbol Assembles the following section of code if the speciﬁed has been deﬁned.
Page 65: File File
Chapter 8. Assembler Directives .ifnes string1 string2 Like , but the sense of the test is reversed: this assembles the following section of code .ifeqs if the two strings are not the same. 8.46. .incbin " "[, file skip count directive includes verbatim at the current location.
Page 66: Symbol
Chapter 8. Assembler Directives is equivalent to assembling move d1,sp@- move d2,sp@- move d3,sp@- 8.51..irpc symbol values Evaluate a sequence of statements assigning different values to . The sequence of statements symbol starts at the directive, and is terminated by an directive.
Page 67: Mri Val
Chapter 8. Assembler Directives 8.54. .line line-number Change the logical line number. must be an absolute expression. The next line has that line-number logical line number. Therefore any other statements on the current line (after a statement separator character) are reported as on logical line number - 1.
Page 68: Expressions
Chapter 8. Assembler Directives 8.58. .list Control (in conjunction with the directive) whether or not assembly listings are generated. .nolist These two directives maintain an internal counter (which is zero initially). increments the .list counter, and decrements it. Assembly listings are generated whenever the counter is greater .nolist than zero.
Page 69: Altmacro
Chapter 8. Assembler Directives .macro reserve_str p1=0 p2 Begin the deﬁnition of a macro called , with two arguments. The ﬁrst argu- reserve_str ment has a default value, but not the second. After the deﬁnition is complete, you can call the macro either as (with evaluating to...
Page 70: New-Lc
Chapter 8. Assembler Directives Expression results as strings You can write to evaluate the expression and use the result as a string. expr expr 8.62. .noaltmacro Disable alternate macro mode. Section 8.61 .altmacro 8.63. .nolist Control (in conjunction with the directive) whether or not assembly listings are generated.
Page 71: P2Align[Wl] Abs-Expr
Chapter 8. Assembler Directives The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by this alignment directive. If doing the alignment would require skipping more bytes than the speciﬁed maximum, then the alignment is not done at all.
Page 72: Columns
Chapter 8. Assembler Directives If you do not use , listings use a default line-count of 60. You may omit the comma and .psize speciﬁcation; the default width is 200 columns. columns generates formfeeds whenever the speciﬁed number of lines is exceeded (or whenever you explic- itly request one, using .eject If you specify...
Page 73: Coff Version
Chapter 8. Assembler Directives 8.76. .sbttl " " subheading as the title (third line, immediately after the title line) when generating assembly subheading listings. This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page.
Page 74: Elf Version
Chapter 8. Assembler Directives shared section (meaningful for PE targets) ignored. (For compatibility with the ELF version) If no ﬂags are speciﬁed, the default ﬂags depend upon the section name. If the section name is not recognized, the default will be for the section to be loaded and writable. Note the ﬂags remove attributes from the section, rather than adding them, so if they are used on their own it will be as if no ﬂags had been speciﬁed at all.
Page 75 Chapter 8. Assembler Directives @progbits section contains data @nobits section does not contain data (i.e., section only occupies space) @note section contains data which is used by things other than the program @init_array section contains an array of pointers to init functions @fini_array section contains an array of pointers to ﬁnish functions @preinit_array...
Page 76: Expression
Chapter 8. Assembler Directives If no ﬂags are speciﬁed, the default ﬂags depend upon the section name. If the section name is not recognized, the default will be for the section to have none of the above ﬂags: it will not be allocated in memory, nor writable, nor executable.
Page 77: Set .Short .Single .Size
Chapter 8. Assembler Directives 8.81. .single flonums This directive assembles zero or more ﬂonums, separated by commas. It has the same effect as . The exact kind of ﬂoating point numbers emitted depends on how is conﬁgured. Chapter .float 9 Machine Dependent Features. 8.82.
Page 78: Stabd, .Stabn, .Stabs
Chapter 8. Assembler Directives Warning: has a completely different meaning for HPPA targets; use as a substitute. See .space .block [HP9000 Series 800 Assembly Language Reference Manual] (HP 92432-90001) for the meaning of the directive. Section 19.5 HPPA Assembler Directives, for a summary. .space On the AMD 29K, this directive is ignored;...
Page 79: Name
Chapter 8. Assembler Directives .stabs string type other desc value All ﬁve ﬁelds are speciﬁed. 8.87. " " .string Copy the characters in to the object ﬁle. You may specify more than one string to copy, separated by commas. Unless otherwise speciﬁed for a particular machine, the assembler marks the end of each string with a 0 byte.
Page 80: Heading
Chapter 8. Assembler Directives the name of a node speciﬁed in the version script supplied to the linker when building a shared library. If you are attempting to override a versioned symbol from a shared library, then should nodename correspond to the nodename of the symbol you are trying to override. If the symbol is not deﬁned within the ﬁle being assembled, all references to will be...
Page 81: Coff Version
Chapter 8. Assembler Directives 8.94.1. COFF Version For COFF targets, this directive is permitted only within pairs. It is used like this: .def .endef .type This records the integer as the type attribute of a symbol table entry. is associated only with COFF format output; when is conﬁgured for output, it .type...
Page 82: Expressions
Chapter 8. Assembler Directives 8.97. .version " " string This directive creates a section and places into it an ELF formatted note of type NT_VERSION. .note The note’s name is set to string 8.98. .vtable_entry table offset This directive ﬁnds or creates a symbol and creates a relocation for it with an table...
Page 83: Deprecated Directives
Chapter 8. Assembler Directives immediately before the next label. This secondary jump table is preceded by a short-jump to the ﬁrst byte after the secondary table. This short-jump prevents the ﬂow of control from accidentally falling into the new table. Inside the table is a long-jump to .
Page 84 Chapter 8. Assembler Directives...
Page 85: Machine Dependent Features
Chapter 9. Machine Dependent Features The machine instruction sets are (almost by deﬁnition) different on each machine where runs. Floating point representations vary as well, and often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of support special pseudo-instructions for branch optimization.
Page 86 Chapter 9. Machine Dependent Features...
Page 87: Amd 29K Dependent Features
Chapter 10. AMD 29K Dependent Features 10.1. Options has no additional command-line options for the AMD 29K family. 10.2. Syntax 10.2.1. Macros The macro syntax used on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Speciﬁcation.
Page 88: Floating Point
Chapter 10. AMD 29K Dependent Features exop 10.3. Floating Point The AMD 29K family uses ieee ﬂoating-point numbers. 10.4. AMD 29K Machine Directives .block size fill This directive emits bytes, each of value . Both are absolute expres- size fill size fill sions.
Page 89: Alpha Dependent Features
Chapter 11. Alpha Dependent Features 11.1. Notes The documentation here is primarily for the ELF object format. also supports the ECOFF and EVAX formats, but features speciﬁc to these formats are not yet documented. 11.2. Options This option speciﬁes the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message.
Page 90: Syntax
Chapter 11. Alpha Dependent Features -32addr These options are ignored for backward compatibility. 11.3. Syntax The assembler syntax closely follow the Alpha Reference Manual; assembler directives and general syntax closely follow the OSF/1 and OpenVMS syntax, with a few differences for ELF. 11.3.1.
Page 91 Chapter 11. Alpha Dependent Features !lituse_base! Used with any memory format instruction (e.g. ) to indicate that the literal is used for an address load. The offset ﬁeld of the instruction must be zero. During relaxation, the code may be altered to use a gp-relative load.
Page 92: Floating Point
Chapter 11. Alpha Dependent Features !samegp Used with any branch format instruction to skip the GP load at the target address. The referenced symbol must have the same GP as the source object ﬁle, and it must be declared to either not use or perform a standard GP load in the ﬁrst two instructions via the directive.
Page 93 Chapter 11. Alpha Dependent Features .arch Speciﬁes the target processor. This is equivalent to the command-line option. Options, for a list of values for .ent function Mark the beginning of . An optional number may follow for compatibility with the function OSF/1 assembler, but is ignored.
Page 94 Chapter 11. Alpha Dependent Features .gprel32 expression Computes the difference between the address in and the GP for the current object expression ﬁle, and stores it in 4 bytes. In addition to being smaller than a full 8 byte address, this also does not require a dynamic relocation when used in a shared library.
Page 95: Opcodes
Chapter 11. Alpha Dependent Features 11.6. Opcodes detailed information Alpha machine instruction set, ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdfAlpha Architecture Handbook.
Page 96 Chapter 11. Alpha Dependent Features...
Page 97: Arc Dependent Features
Chapter 12. ARC Dependent Features 12.1. Options -marc[5|6|7|8] This option selects the core processor variant. Using is the same as , which is also -marc -marc6 the default. arc5 Base instruction set. arc6 Jump-and-link (jl) instruction. No requirement of an instruction between setting ﬂags and conditional jump.
Page 98: Register Names
Chapter 12. ARC Dependent Features 12.2.2. Register Names *TODO* 12.3. Floating Point The ARC core does not currently have hardware ﬂoating point support. Software ﬂoating point support is provided by and uses ieee ﬂoating-point numbers. 12.4. ARC Machine Directives The ARC version of supports the following additional machine directives: .2byte expressions...
Page 99: Opcodes
Chapter 12. ARC Dependent Features .option arc|arc5|arc6|arc7|arc8 directive must be followed by the desired core version. Again is an alias for .option arc6 Note: the directive overrides the command line option ; a warning is emitted .option -marc when the version is not consistent between the two - even for the implicit default core version (arc6).
Page 100 Chapter 12. ARC Dependent Features...
Page 101: Arm Dependent Features
Chapter 13. ARM Dependent Features 13.1. Options -mcpu= ...] processor extension This option speciﬁes the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: arm1 arm2...
Page 102 Chapter 13. ARM Dependent Features -mthumb This option speciﬁes that the assembler should start assembling Thumb instructions; that is, it should behave as though the ﬁle starts with a directive. .code 16 -mthumb-interwork This option speciﬁes that the output generated by the assembler should be marked as supporting interworking.
Page 103: Syntax
Chapter 13. ARM Dependent Features -moabi This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF speciﬁcations, rather than the default conventions which are based on the ﬁnal release of the ARM-ELF speciﬁcations. 13.2.
Page 104: Opcodes
Chapter 13. ARM Dependent Features .code [16|32] This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM. .thumb This performs the same action as .code 16 .arm This performs the same action as .code 32 .force_thumb This directive forces the selection of Thumb instructions, even if the target processor does not...
Page 105: Mapping Symbols
Chapter 13. ARM Dependent Features This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0. register expression If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions.
Page 106 Chapter 13. ARM Dependent Features speciﬁcation is not implemented. This is because they have been dropped from the new EABI and so tools cannot rely upon their presence.
Page 107: Cris Dependent Features
Chapter 14. CRIS Dependent Features 14.1. Command-line Options The CRIS version of has these machine-dependent command-line options. The format of the generated object ﬁles can be either ELF or a.out, speciﬁed by the command-line options . The default is ELF (criself), unless -emulation=crisaout -emulation=criself has been conﬁgured speciﬁcally for a.out by using the conﬁguration name...
Page 108: Special Characters
Chapter 14. CRIS Dependent Features 14.3.1. Special Characters The character is a line comment character. It starts a comment if and only if it is placed at the beginning of a line. character starts a comment anywhere on the line, causing all characters up to the end of the line to be ignored.
Page 109: Register Names
Chapter 14. CRIS Dependent Features be a function entry and will be resolved by the run-time resolver as with . The relocation is . Example: R_CRIS_32_GOTPLT jsr [$r0+fnname:GOTPLT] GOTPLT16 A variant of giving a 16-bit value. Its relocation name is .
Page 110 Chapter 14. CRIS Dependent Features...
Page 111: D10V Dependent Features
Chapter 15. D10V Dependent Features 15.1. D10V Options The Mitsubishi D10V version of has a few machine dependent options. The D10V can often execute two sub-instructions in parallel. When this option is used, will attempt to optimize its output by detecting when instructions can be executed in parallel. -nowarnswap To optimize execution performance, will sometimes swap the order of instructions.
Page 112: Special Characters
Chapter 15. D10V Dependent Features If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section. 15.2.3. Special Characters are the line comment characters.
Page 113: Register Names
Chapter 15. D10V Dependent Features 15.2.4. Register Names You can use the predeﬁned symbols through to refer to the D10V registers. You can also use as an alias for . The accumulators are . There are special register-pair names that may optionally be used in opcodes that require even-numbered registers.
Page 114: Addressing Modes
Chapter 15. D10V Dependent Features Flag 1 Carry ﬂag 15.2.5. Addressing Modes understands the following addressing modes for the D10V. in the following refers to any of the numbered registers, but not the control registers. Register direct Register indirect Register indirect with post-increment Register indirect with post-decrement @-SP Register indirect with pre-decrement...
Page 115: Floating Point
Chapter 15. D10V Dependent Features 15.3. Floating Point The D10V has no hardware ﬂoating point, but the directives generates ieee .float .double ﬂoating-point numbers for compatibility with other development tools. 15.4. Opcodes For detailed information on the D10V machine instruction set, see [D10V Architecture: A VLIW Mi- croprocessor for Multimedia Applications] (Mitsubishi Electric Corp.).
Page 116 Chapter 15. D10V Dependent Features...
Page 117: D30V Dependent Features
Chapter 16. D30V Dependent Features 16.1. D30V Options The Mitsubishi D30V version of has a few machine dependent options. The D30V can often execute two sub-instructions in parallel. When this option is used, will attempt to optimize its output by detecting when instructions can be executed in parallel. When this option is used, will issue a warning every time it adds a nop instruction.
Page 118: Special Characters
Chapter 16. D30V Dependent Features 16.2.3. Special Characters are the line comment characters. Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially unless you use the option. To specify the executing order, use the following symbols: Sequential with instruction on the left ﬁrst.
Page 119: Guarded Execution
Chapter 16. D30V Dependent Features Since has no special meaning, you may use it in symbol names. 16.2.4. Guarded Execution supports the full range of guarded execution directives for each instruction. Just append the direc- tive after the instruction proper. The directives are: Execute the instruction if ﬂag f0 is true.
Page 120 Chapter 16. D30V Dependent Features rpt_e Repeat End address mod_s Modulo Start address mod_e Modulo End address Instruction Break Address Flag 0 Flag 1 Flag 2 Flag 3 Flag 4 Flag 5 Flag 6 Flag 7 Same as ﬂag 4 (saturation ﬂag) Same as ﬂag 5 (overﬂow ﬂag) Same as ﬂag 6 (sticky overﬂow ﬂag) Same as ﬂag 7 (carry/borrow ﬂag)
Page 121: Addressing Modes
Chapter 16. D30V Dependent Features Same as ﬂag 7 (carry/borrow ﬂag) 16.2.6. Addressing Modes understands the following addressing modes for the D30V. in the following refers to any of the numbered registers, but not the control registers. Register direct Register indirect Register indirect with post-increment Register indirect with post-decrement @-SP...
Page 122 Chapter 16. D30V Dependent Features...
Page 123: H8/300 Dependent Features
Chapter 17. H8/300 Dependent Features 17.1. Options has no additional command-line options for the Renesas (formerly Hitachi) H8/300 family. 17.2. Syntax 17.2.1. Special Characters is the line comment character. can be used instead of a newline to separate statements. Therefore you may not use in symbol names on the H8/300.
Page 124: Floating Point
Chapter 17. H8/300 Dependent Features Register indirect with post-increment Register indirect with pre-decrement Absolute address . (The address size only makes sense on the H8/300H.) Immediate data . You may specify the , or for clarity, if you wish; but neither requires this nor uses it--the data size required is taken from context.
Page 125: Opcodes
Chapter 17. H8/300 Dependent Features .h8300sn Recognize and emit additional instructions for the H8S variant in normal mode, and also make emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family. .int On the H8/300 family (including the H8/300H) directives generate 16-bit numbers.
Page 126 Chapter 17. H8/300 Dependent Features...
Page 127: H8/500 Dependent Features
Chapter 18. H8/500 Dependent Features 18.1. Options has no additional command-line options for the Renesas (formerly Hitachi) H8/500 family. 18.2. Syntax 18.2.1. Special Characters is the line comment character. can be used instead of a newline to separate statements. Since has no special meaning, you may use it in symbol names.
Page 128: Addressing Modes
Chapter 18. H8/500 Dependent Features 18.2.3. Addressing Modes as understands the following addressing modes for the H8/500: Register direct Register indirect @(d:8, R Register indirect with 8 bit signed displacement @(d:16, R Register indirect with 16 bit signed displacement Register indirect with pre-decrement Register indirect with post-increment 8 bit absolute address 16 bit absolute address...
Page 129: Opcodes
Chapter 18. H8/500 Dependent Features 18.5. Opcodes For detailed information on the H8/500 machine instruction set, see [H8/500 Series Programming Manual] (Renesas M21T001). implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family.
Page 130 Chapter 18. H8/500 Dependent Features...
Page 131: Hppa Dependent Features
Chapter 19. HPPA Dependent Features 19.1. Notes As a back end for gnu cc has been throughly tested and should work extremely well. We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers.
Page 132 Chapter 19. HPPA Dependent Features 19.5. HPPA Assembler Directives for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only brieﬂy. For detailed information on HPPA-speciﬁc assembler directives, see [HP9000 Series 800 Assembly Language Reference Manual] (HP 92432-90001). does not support the following assembler directives described in the HP manual: .endm .liston...
Page 133 Chapter 19. HPPA Dependent Features .export ] [ , name param Make a procedure available to callers. , if present, must be one of name absolute code (ELF only, not SOM), , or data entry data entry millicode plabel pri_prog sec_prog , if present, provides either relocation information for the procedure arguments and result, param...
Page 134 Chapter 19. HPPA Dependent Features .spnum secnam Allocate four bytes of storage, and initialize them with the section number of the section named . (You can deﬁne the section number with the HPPA directive.) secnam .space .string " " Copy the characters in the string to the object ﬁle.
Page 135: Opcodes
Chapter 19. HPPA Dependent Features .version " " Write as version identiﬁer in object code. 19.6. Opcodes For detailed information on the HPPA machine instruction set, see [PA-RISC Architecture and In- struction Set Reference Manual] (HP 09740-90039).
Page 136 Chapter 19. HPPA Dependent Features...
Page 137: Esa/390 Dependent Features
Chapter 20. ESA/390 Dependent Features 20.1. Notes The ESA/390 port is currently intended to be a back-end for the gnu cc compiler. It is not HLASM compatible, although it does support a subset of some of the HLASM directives. The only supported binary ﬁle format is ELF;...
Page 138: Floating Point
Chapter 20. ESA/390 Dependent Features AH r0,=H’42’ ME r6,=E’3.1416’ MD r6,=D’3.14159265358979’ O r6,=XL4’cacad0d0’ .ltorg should all behave as expected: that is, an entry in the literal pool will be created (or reused if it already exists), and the instruction operands will be the displacement into the literal pool using the current base register (as last declared with the directive).
Page 139: Opcodes
Chapter 20. ESA/390 Dependent Features is speciﬁed, then the subsequent must be put in the same section; otherwise an error will .ltorg result. Thus, for example, the following code uses to address branch targets and to address the literal pool, which has been written to the section.
Page 140 Chapter 20. ESA/390 Dependent Features...
Page 141: Dependent Features
Chapter 21. 80386 Dependent Features The i386 version supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits. 21.1. Options The i386 version of has a few machine dependent options: -32 | -64 Select the word size, either 32 bits or 64 bits.
Page 142: Instruction Naming
Chapter 21. 80386 Dependent Features Immediate form long jumps and calls are in AT&T syntax; • lcall/ljmp $ section offset the Intel syntax is . Also, the far return instruction is call/jmp far lret section offset in AT&T syntax; Intel syntax is ret far stack-adjust stack-adjust...
Page 143: Instruction Preﬁxes
Chapter 21. 80386 Dependent Features the 6 section registers (code section), (data section), (stack section), , and • the 3 processor control registers , and • %cr0 %cr2 %cr3 the 6 debug registers , and • %db0 %db1 %db2 %db3 %db6 %db7 the 2 test registers...
Page 144: Memory References
Chapter 21. 80386 Dependent Features The bus lock preﬁx inhibits interrupts during execution of the instruction it precedes. (This is • lock only valid with certain instructions; see a 80386 manual for details). The wait for coprocessor preﬁx waits for the coprocessor to complete the current instruction. •...
Page 145: Handling Of Jump Instructions
Chapter 21. 80386 Dependent Features AT&T: ; Intel %gs:foo gs:foo This selects the contents of the variable with section register being section Absolute (as opposed to PC relative) call and jump operands must be preﬁxed with . If no speciﬁed, always chooses PC relative addressing for jump/call labels.
Page 146: Intel's Mmx And Amd's 3Dnow! Simd Operations
Chapter 21. 80386 Dependent Features Integer constructors are , and for the 16-, 32-, and 64-bit integer • .word .long .int .quad formats. The corresponding instruction mnemonic sufﬁxes are (single), (long), and (quad). As with the 80-bit real format, the 64-bit format is only present in the (load quad integer fildq...
Page 147: At&T Syntax Bugs
Chapter 21. 80386 Dependent Features 21.11. AT&T Syntax bugs The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate ﬂoating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we’re stuck with it. For example fsub %st,%st(3) results in...
Page 148 Chapter 21. 80386 Dependent Features multiply; the expanding multiply would clobber the register, and this would confuse output. %edx to get the 64-bit product in imul %ebx %edx:%eax We have added a two operand form of when the ﬁrst operand is an immediate mode expression imul and the second operand is a register.
Page 149: Intel I860 Dependent Features
Chapter 22. Intel i860 Dependent Features 22.1. i860 Notes This is a fairly complete i860 assembler which is compatible with the UNIX System V/860 Release 4 assembler. However, it does not currently support SVR4 PIC (i.e., @GOT, @GOTOFF, @PLT Like the SVR4/860 assembler, the output object format is ELF32. Currently, this is the only supported object format.
Page 150: I860 Machine Directives
Chapter 22. Intel i860 Dependent Features -mxp Enable support for the i860XP instructions and control registers. By default, this option is dis- abled so that only the base instruction set (i.e., i860XR) is supported. -mintel-syntax The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the Intel syntax. 22.3.
Page 151 Chapter 22. Intel i860 Dependent Features For example, the pseudo-instruction will be expanded into: ld.b addr_exp(%rx),%rn orh addr_exp@ha,%rx,%r31 ld.l addr_exp@l(%r31),%rn The analogous expansions apply to , and as well. ld.x, st.x, fld.x, pfld.x, fst.x pst.x Signed large immediate with add/subtract: •...
Page 152 Chapter 22. Intel i860 Dependent Features...
Page 153: Intel 80960 Dependent Features
Chapter 23. Intel 80960 Dependent Features 23.1. i960 Command-line Options -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC Select the 80960 architecture. Instructions or features not supported by the selected architecture cause fatal errors. is equivalent to is equivalent to .
Page 154: Floating Point
Chapter 23. Intel 80960 Dependent Features This option does not affect the Compare-and-Jump instructions; the code emitted for them is always adjusted when necessary (depending on displacement size), regardless of whether you -no-relax 23.2. Floating Point generates ieee ﬂoating-point numbers for the directives , and .float .double...
Page 155: Compare-And-Branch
Chapter 23. Intel 80960 Dependent Features Some opcodes are processed beyond simply emitting a single corresponding instruction: , and callj Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits. 23.4.1. callj You can write to have the assembler or the linker determine the most appropriate form of sub- callj routine call: , or...
Page 156 Chapter 23. Intel 80960 Dependent Features...
Page 157: Ip2K Dependent Features
Chapter 24. IP2K Dependent Features 24.1. IP2K Options The Ubicom IP2K version of has a few machine dependent options: -mip2022ext can assemble the extended IP2022 instructions, but it will only do so if this is speciﬁcally allowed via this command line option. -mip2022 This option restores the assembler’s default behaviour of not permitting the extended IP2022 instructions to be assembled.
Page 158 Chapter 24. IP2K Dependent Features...
Page 159: M32R Dependent Features
Chapter 25. M32R Dependent Features 25.1. M32R Options The Renease M32R version of has a few machine dependent options: -m32rx can assemble code for several different members of the Renesas M32R family. Normally the default is to assemble code for the M32R microprocessor. This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions.
Page 160 Chapter 25. M32R Dependent Features -no-bitinst This option disables the support for the extended bit-ﬁeld instructions provided by the M32R2. If this support needs to be re-enabled the -bitinst switch can be used to restore it. This option tells the assembler to attempt to optimize the instructions that it produces. This includes ﬁlling delay slots and converting sequential instructions into parallel ones.
Page 161: M32R Directives
Chapter 25. M32R Dependent Features -Wuh This is a shorter synonym for the -warn-unmatched-high option. -Wnuh This is a shorter synonym for the -no-warn-unmatched-high option. 25.2. M32R Directives The Renease M32R version of has a few architecture speciﬁc directives: expression directive computes the value of its expression and places the lower 16-bits of the result into the immediate-ﬁeld of the instruction.
Page 162: M32R Warnings
Chapter 25. M32R Dependent Features .m32r The directive performs a similar thing as the -m32r command line option. It tells the assembler to only accept M32R instructions from now on. An instructions from later M32R architectures are refused. .m32rx The directive performs a similar thing as the -m32rx command line option. It tells the assembler to start accepting the extra instructions in the M32RX ISA as well as the ordinary M32R ISA.
Page 163 Chapter 25. M32R Dependent Features unknown instruction This message is produced when the assembler encounters an instruction which it does not recog- nise. only the NOP instruction can be issued in parallel on the m32r This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the command line ﬂag has not been speciﬁed.
Page 164 Chapter 25. M32R Dependent Features...
Page 165: M680X0 Dependent Features
Chapter 26. M680x0 Dependent Features 26.1. M680x0 Options The Motorola 680x0 version of has a few machine dependent options: You can use the option to shorten the size of references to undeﬁned symbols. If you do not use the option, references to undeﬁned symbols are wide enough for a full (32 bits).
Page 166 Chapter 26. M680x0 Dependent Features -pcrel Always keep branches PC-relative. In the M680x0 architecture all branches are deﬁned as PC- relative. However, on some processors they are limited to word displacements maximum. When needs a long branch that is not available, it normally emits an absolute jump instead. This option disables this substitution.
Page 167 Chapter 26. M680x0 Dependent Features -mcpu32 -m68330 -m68331 -m68332 -m68333 -m68334 -m68336 -m68340 -m68341 -m68349 -m68360 Assemble for the CPU32 family of chips. -m5200 -m5202 -m5204 -m5206 -m5206e -m521x -m5249 -m528x -m5307 -m5407 -m547x -m548x -mcfv4 -mcfv4e Assemble for the ColdFire family of chips. -m68881 -m68882 Assemble 68881 ﬂoating point instructions.
Page 168: Syntax
Chapter 26. M680x0 Dependent Features 26.2. Syntax This syntax for the Motorola 680x0 was developed at mit. The 680x0 version of uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, is equivalent to movl mov.l In the following table...
Page 169: Motorola Syntax
Chapter 26. M680x0 Dependent Features 26.3. Motorola Syntax The standard Motorola syntax for this chip differs from the syntax already discussed (Section 26.2 Syntax). can accept Motorola syntax for operands, even if mit syntax is used for other operands in the same instruction.
Page 170: Floating Point
Chapter 26. M680x0 Dependent Features 26.4. Floating Point Packed decimal (P) format ﬂoating literals are not supported. Feel free to add the code! The ﬂoating point formats generated by directives are these. .float precision ﬂoating point constants. Single .double precision ﬂoating point constants. Double .extend .ldouble...
Page 171 Chapter 26. M680x0 Dependent Features 68020 68000/10, not PC-relative OK Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP +------------------------------------------------------------ jbsr |bsrs bsrw bsrl jra |bras braw bral jXX |bXXs bXXw bXXl bNXs;jmp dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp fjXX | N/A fbXXw fbXXl XX: condition...
Page 172: Special Characters
Chapter 26. M680x0 Dependent Features If, however, long branches are not available and the option is not given, emits -pcrel bras oo2 oo1:jmp foo oo2: This family includes fjne fjeq fjge fjlt fjgt fjle fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge...
Page 173: M68Hc11 And M68Hc12 Dependent Features
Chapter 27. M68HC11 and M68HC12 Dependent Features 27.1. M68HC11 and M68HC12 Options The Motorola 68HC11 and 68HC12 version of have a few machine dependent options. -m68hc11 This option switches the assembler in the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics.
Page 174: Syntax
Chapter 27. M68HC11 and M68HC12 Dependent Features -short-branchs option turns off the translation of relative branches into absolute branches -short-branchs when the branch offset is out of range. By default transforms the relative branch ( ) into an absolute branch when the offset is out of the -128 ..
Page 175 Chapter 27. M68HC11 and M68HC12 Dependent Features Address Register number number may be omitted in which case 0 is assumed. number Direct Addressing mode , or symbol digits Absolute , or symbol digits The M68HC12 has other more complex addressing modes. All of them are supported and they are represented below: Constant Offset Indexed Addressing Mode number...
Page 176: Symbolic Operand Modiﬁers
Chapter 27. M68HC11 and M68HC12 Dependent Features 27.3. Symbolic Operand Modiﬁers The assembler supports several modiﬁers when using symbol addresses in 68HC11 and 68HC12 instruction operands. The general syntax is the following: %modifier(symbol) %addr This modiﬁer indicates to the assembler and linker to use the 16-bit physical address correspond- ing to the symbol.
Page 177: Floating Point
Chapter 27. M68HC11 and M68HC12 Dependent Features .relax The relax directive is used by the to emit a speciﬁc relocation to mark a group of GNU Compiler instructions for linker relaxation. The sequence of instructions within the group must be known to the linker so that relaxation can be performed.
Page 178 Chapter 27. M68HC11 and M68HC12 Dependent Features Displacement Width +-------------------------------------------------------------+ Options --short-branchs --force-long-branchs +--------------------------+----------------------------------+ Op |BYTE WORD | BYTE WORD +--------------------------+----------------------------------+ bsr | bsr pc-rel error " " " bra | bra pc-rel error " " " jbsr | bsr pc-rel | bsr pc-rel...
Page 179: Motorola M88K Dependent Features
Chapter 28. Motorola M88K Dependent Features 28.1. M88K Machine Directives The M88K version of the assembler supports the following machine directives: .align This directive aligns the section program counter on the next 4-byte boundary. .dfloat expr This assembles a double precision (64-bit) ﬂoating point constant. .ffloat expr This assembles a single precision (32-bit) ﬂoating point constant.
Page 180 Chapter 28. Motorola M88K Dependent Features...
Page 181: Mips Dependent Features
Chapter 29. MIPS Dependent Features for mips architectures supports several different mips processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For information about the mips instruction set, see [MIPS RISC Architecture], by Kane and Heindrich (Prentice-Hall). For an overview of mips assembly conventions, see "Appendix D: Assembly Language Programming"...
Page 182 Chapter 29. MIPS Dependent Features -mgp64 Assume that 64-bit general purpose registers are available. This is provided in the interests of symmetry with -gp32. -mips16 -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting at the start .set mips16 of the assembly ﬁle.
Page 183: Mips Ecoff Object Code
Chapter 29. MIPS Dependent Features 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, mips32-4k, sb1 -mtune= Schedule and tune for a particular MIPS cpu. Valid values are identical to -march= -mabi=...
Page 184: Directives For Debugging Information
Chapter 29. MIPS Dependent Features uses . Passing prevents it from using the register on the basis of object size (but -G 0 the assembler uses for objects in in any case). The size of an object in the .sdata sbss .bss section is set by the...
Page 185: Directives To Save And Restore Options
Chapter 29. MIPS Dependent Features 29.7. Directives to save and restore options The directives may be used to save and restore the current settings for all .set push .set pop the options which are controlled by . The directive saves the current settings on a .set .set push stack.
Page 186 Chapter 29. MIPS Dependent Features...
Page 187: Mmix Dependent Features
Chapter 30. MMIX Dependent Features 30.1. Command-line Options The MMIX version of has some machine-dependent options. When is speciﬁed, only the register names speciﬁed in Section -fixed-special-register-names 30.3.3 Register names are recognized in the instructions You can use the to make all symbols global. This option is useful when -globalize-symbols splitting up a program into several ﬁles.
Page 188: Instruction Expansion
Chapter 30. MMIX Dependent Features 30.2. Instruction expansion When encounters an instruction with an operand that is either not known or does not ﬁt the operand size of the instruction, (and ) will expand the instruction into a sequence of instructions seman- tically equivalent to the operand ﬁtting the instruction.
Page 189: Symbols
Chapter 30. MMIX Dependent Features 30.3.2. Symbols The character is permitted in identiﬁers. There are two exceptions to it being treated as any other symbol character: if a symbol begins with , it means that the symbol is in the global namespace and that the current preﬁx should not be prepended to that symbol.
Page 190 Chapter 30. MMIX Dependent Features An example, which sets the label to the current location, and updates the current location prev to eight bytes forward: prev LOC @+8 When a LOC has a constant as its operand, a symbol __.MMIX.start..text is deﬁned depending on the address as mentioned above.
Page 191 Chapter 30. MMIX Dependent Features buffer1 BYTE 0,0,0,0,0 buffer2 BYTE 0,0,0,0,0 tmpreg GREG buffer1 LDOU $42,tmpreg,(buffer2-buffer1) Global registers allocated with this directive are allocated in order higher-to-lower within a ﬁle. Other than that, the exact order of register allocation and elimination is undeﬁned. For example, the order is undeﬁned when more than one ﬁle with such directives are linked together.
Page 192: Mmixal
Chapter 30. MMIX Dependent Features 30.4. Differences to mmixal The binutils combination has a few differences in function compared to (Section mmixal 30.4 Differences to mmixal The replacement of a symbol with a GREG-allocated register is not handled the exactly same way in as in .
Page 193 Chapter 30. MMIX Dependent Features silly.mms LOC to a previous address. sim.mms Redeﬁnes symbol Done test.mms Uses the serial operator &...
Page 194 Chapter 30. MMIX Dependent Features...
Page 195: Msp 430 Dependent Features
Chapter 31. MSP 430 Dependent Features 31.1. Options has only -m ﬂag which selects the mpu arch. Currently has no effect. 31.2. Syntax 31.2.1. Macros The macro syntax used on the MSP 430 is like that described in the MSP 430 Family Assembler Speciﬁcation.
Page 196: Assembler Extensions
Chapter 31. MSP 430 Dependent Features Register names cannot be used as register names and will be treated as variables. Use , and instead. 31.2.4. Assembler Extensions As destination operand being treated as 0(rn) 0(rN) As source operand being treated as jCOND +N Skips next N bytes followed by jump instruction and equivalent to jCOND $+N+2...
Page 197: Floating Point
Chapter 31. MSP 430 Dependent Features bleu label A polymorph instruction which is jeq label; jlo label jeq +2; jhs +4; br label ble label A polymorph instruction which is jeq label; jl label jeq +2; jge +4; br label jump label A polymorph instruction which is jmp label...
Page 198 Chapter 31. MSP 430 Dependent Features We deﬁne new section which holds all proﬁling information. We deﬁne new pseudo .profiler operation which will instruct assembler to add new proﬁle entry to the object ﬁle. Proﬁle .profiler should take place at the present address. Pseudo operation format: .profiler flags,function_to_profile [, cycle_corrector, extra] where:...
Page 199 Chapter 31. MSP 430 Dependent Features extra parameter saved (a constant value like frame size) function_to_profile a function address cycle_corrector a value which should be added to the cycle counter, zero if omitted. extra any extra parameter, zero if omitted. For example: .global fxx .type fxx,@function...
Page 200 Chapter 31. MSP 430 Dependent Features...
Page 201: Dependent Features
Chapter 32. PDP-11 Dependent Features 32.1. Options The PDP-11 version of has a rich set of machine dependent options. 32.1.1. Code Generation Options -mpic | -mno-pic Generate position-independent (or position-dependent) code. The default is to generate position-independent code. 32.1.2. Instruction Set Extension Options These options enables or disables the use of extensions over the base line instruction set as introduced by the ﬁrst PDP-11 CPU: the KA11.
Page 202: Cpu Model Options
Chapter 32. PDP-11 Dependent Features -mfis | -mkev11 -mno-fis | -mno-kev11 Enable (or disable) the use of the KEV11 ﬂoating-point instructions: , and FADD FDIV FMUL FSUB -mfpp | -mfpu | -mfp-11 -mno-fpp | -mno-fpu | -mno-fp-11 Enable (or disable) the use of FP-11 ﬂoating-point instructions: ABSF ADDF CFCC...
Page 203: Machine Model Options
Chapter 32. PDP-11 Dependent Features -mkd11b KD11-B CPU. Base line instruction set only. -mkd11d KD11-D CPU. Base line instruction set only. -mkd11e KD11-E CPU. Enable extended instruction set, , and MFPS MTPS -mkd11f | -mkd11h | -mkd11q KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction set, , and MFPS MTPS...
Page 204: Assembler Directives
Chapter 32. PDP-11 Dependent Features -m11/21 Same as -mt11 -m11/23 | -m11/24 Same as -mf11 -m11/34 Same as -mkd11e -m11/34a Ame as -mkd11e -mfpp -m11/35 | -m11/40 Same as -mkd11a -m11/44 Same as -mkd11z -m11/45 | -m11/50 | -m11/55 | -m11/70 Same as -mkb11 -m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94...
Page 205: Instruction Naming
Chapter 32. PDP-11 Dependent Features Comments are started with a or a character, and extend to the end of the line. (FIXME: clash with immediates?) 32.4. Instruction Naming Some instructions have alternative names. BHIS L2DR L3DR TRAP 32.5. Synthetic Instructions synthetic instructions are not supported yet.
Page 206 Chapter 32. PDP-11 Dependent Features...
Page 207: Picojava Dependent Features
Chapter 33. picoJava Dependent Features 33.1. Options has two additional command-line options for the picoJava architecture. This option selects little endian data output. This option selects big endian data output.
Page 208 Chapter 33. picoJava Dependent Features...
Page 209: Powerpc Dependent Features
Chapter 34. PowerPC Dependent Features 34.1. Options The PowerPC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip’s architecture reference manual. The following table lists all available PowerPC options.
Page 210: Powerpc Assembler Directives
Chapter 34. PowerPC Dependent Features -mpower4 Generate code for Power4 architecture. -mcom Generate code Power/PowerPC common instructions. -many Generate code for any architecture (PWR/PWRX/PPC). -mregnames Allow symbolic names for registers. -mno-regnames Do not allow symbolic names for registers. -mrelocatable Support for GCC’s -mrelocatble option. -mrelocatable-lib Support for GCC’s -mrelocatble-lib option.
Page 211: Renesas / Superh Sh Dependent Features
Chapter 35. Renesas / SuperH SH Dependent Features 35.1. Options has following command-line options for the Renesas (formerly Hitachi) / SuperH SH family. -little Generate little endian code. -big Generate big endian code. -relax Alter jump instructions for long displacements. -small Align sections to 4 byte boundaries, not 16.
Page 212: Register Names
Chapter 35. Renesas / SuperH SH Dependent Features 35.2.2. Register Names You can use the predeﬁned symbols to refer to the SH registers. The SH also has these control registers: procedure register (holds return address) program counter mach macl high and low multiply accumulator registers status register global base register vector base register (for interrupt vectors)
Page 213: Floating Point
Chapter 35. Renesas / SuperH SH Dependent Features @(R0, GBR) GBR indexed addr , PC) disp PC relative address (for branch or for addressing memory). The implementation allows you to use the simpler form anywhere a PC relative address is called for; the alternate form is addr supported for compatibility with other assemblers.
Page 214 Chapter 35. Renesas / SuperH SH Dependent Features mov.l , PC) disp...
Page 215: Superh Sh64 Dependent Features
Chapter 36. SuperH SH64 Dependent Features 36.1. Options -isa=sh4 | sh4a Specify the sh4 or sh4a instruction set. -isa=dsp Enable sh-dsp insns, and disable sh3e / sh4 insns. -isa=fp Enable sh2e, sh3e, sh4, and sh4a insn sets. -isa=all Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. -isa=shmedia | -isa=shcompact Specify the default instruction set.
Page 216: Syntax
Chapter 36. SuperH SH64 Dependent Features 36.2. Syntax 36.2.1. Special Characters is the line comment character. You can use instead of a newline to separate statements. Since has no special meaning, you may use it in symbol names. 36.2.2. Register Names You can use the predeﬁned symbols through to refer to the SH64 general registers,...
Page 217: Opcodes
Chapter 36. SuperH SH64 Dependent Features .mode [shmedia|shcompact] .isa [shmedia|shcompact] Specify the ISA for the following instructions (the two directives are equivalent). Note that pro- grams such as rely on symbolic labels to determine when such mode switches occur objdump (by checking the least signiﬁcant bit of the label’s address), so such mode/isa changes should always be followed by a label (in practice, this is true anyway).
Page 218 Chapter 36. SuperH SH64 Dependent Features...
Page 219: Sparc Dependent Features
Chapter 37. SPARC Dependent Features 37.1. Options The SPARC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip’s architecture reference manual. By default, assumes the core instruction set (SPARC v6), but "bumps"...
Page 220: Floating Point
Chapter 37. SPARC Dependent Features You can use the option to make SPARC GAS also issue an error about -enforce-aligned-data misaligned data, just as the SunOS and Solaris assemblers do. option is not the default because gcc issues misaligned data pseudo- -enforce-aligned-data ops when it initializes certain packed data structures (structures deﬁned using the attribute).
Page 221 Chapter 37. SPARC Dependent Features .skip This is functionally identical to the directive. .space .word On the Sparc, the directive produces 32 bit values, instead of the 16 bit values it produces .word on many other machines. .xword On the Sparc V9 processor, the directive produces 64 bit values.
Page 222 Chapter 37. SPARC Dependent Features...
Page 223: Tic54X Dependent Features
Chapter 38. TIC54X Dependent Features 38.1. Options The TMS320C54x version of has a few machine-dependent options. You can use the option to enable extended addressing mode. All addresses will be -mfar-mode assumed to be 16 bits, and the appropriate relocation types will be used. This option is equivalent to using the directive in the assembly code.
Page 224: Local Labels
Chapter 38. TIC54X Dependent Features Subsyms may be deﬁned using the directives (Section 38.9 Directives, Section 38.9 .asg .eval Directives. Expansion is recursive until a previously encountered symbol is seen, at which point substitution stops. In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1 is replaced with x.
Page 225: Math Builtins
Chapter 38. TIC54X Dependent Features Entering or leaving an included ﬁle • The macro scope where the label was deﬁned is exited • 38.7. Math Builtins The following built-in functions may be used to generate a ﬂoating-point value. All return a ﬂoating- point value except , and , which return an integer value.
Page 226 Chapter 38. TIC54X Dependent Features $fmod( expr1 expr2 Returns the ﬂoating point remainder of expr1 expr2 $int( expr Returns 1 if evaluates to an integer, zero otherwise. expr $ldexp( expr1 expr2 Returns the ﬂoating point value * 2 ^ expr1 expr2 $log10( expr...
Page 227: Extended Addressing
Chapter 38. TIC54X Dependent Features $tanh( expr Returns the ﬂoating point hyperbolic tangent of expr $trunc( expr Returns the integer value of truncated towards zero as ﬂoating point. expr 38.8. Extended Addressing pseudo-op is provided for loading the extended addressing bits of a label or address. For example, if an address resides in extended program memory, the value of may be...
Page 228 Chapter 38. TIC54X Dependent Features .byte [,..., value value_n .ubyte [,..., value value_n .char [,..., value value_n .uchar [,..., value value_n Place one or more bytes into consecutive words of the current section. The upper 8 bits of each word is zero-ﬁlled. If a label is used, it points to the word allocated for the ﬁrst byte encountered. .clink ["...
Page 229 Chapter 38. TIC54X Dependent Features .field value size Initialize a bitﬁeld of bits in the current section. If is relocatable, then must size value size be 16. defaults to 16 bits. If does not ﬁt into bits, the value will be truncated. size value size...
Page 230 Chapter 38. TIC54X Dependent Features terminates the loop so that assembly begins after the directive. The optional .break .endloop will cause the loop to terminate only if it evaluates to zero. condition .macro [ ][,... macro_name param1 param_n [.mexit] .endm See the section on macros for more explanation (Section 38.10 Macros.
Page 231 Chapter 38. TIC54X Dependent Features .sslist .ssnolist Controls the inclusion of subsym replacement in the listing output. Ignored. .string " " [,...," "] string string_n .pstring " " [,...," "] string string_n Place 8-bit characters from into the current section. zero-ﬁlls the upper 8 bits string .string...
Page 232: Macros
Chapter 38. TIC54X Dependent Features ] .usect " ", , [,[ ] [, symbol section_name size blocking_flag alignment_flag Reserve space for variables in a named, uninitialized section (similar to .bss). allows .usect deﬁnitions sections independent of .bss. points to the ﬁrst location reserved by this symbol allocation.
Page 233: Memory-Mapped Registers
Chapter 38. TIC54X Dependent Features $lastch( Returns index of the last occurrence of character constant $isdefed( symbol Returns zero if the symbol is not in the symbol table, non-zero otherwise. symbol $ismember( symbol list Assign the ﬁrst member of comma-separated string is reassigned the list symbol...
Page 234 Chapter 38. TIC54X Dependent Features...
Page 235: Z8000 Dependent Features
Chapter 39. Z8000 Dependent Features The Z8000 as supports both members of the Z8000 family: the unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit addresses. When the assembler is in unsegmented mode (speciﬁed with the directive), an address takes unsegm up one word (16 bit) sized register.
Page 236: Addressing Modes
Chapter 39. Z8000 Dependent Features 39.2.3. Addressing Modes as understands the following addressing modes for the Z8000: Register direct: 8bit, 16bit, 32bit, and 64bit registers. Indirect register: @rr in segmented mode, @r in unsegmented mode. addr Direct: the 16 bit or 24 bit address (depending on whether the assembler is in segmented or unsegmented mode) of the operand is in the instruction.
Page 237: Opcodes
Chapter 39. Z8000 Dependent Features .z8002 Generate code for the unsegmented Z8002. name Synonym for .file global Synonym for .global wval Synonym for .word lval Synonym for .long bval Synonym for .byte sval Assemble a string. expects one string literal, delimited by single quotes. It assembles each sval byte of the string into consecutive addresses.
Page 238 Chapter 39. Z8000 Dependent Features...
Page 239: Vax Dependent Features
Chapter 40. VAX Dependent Features 40.1. VAX Command-Line Options The Vax version of accepts any of the following options, gives a warning message that the option was ignored and proceeds. These options are for compatibility with scripts designed for other people’s assemblers.
Page 240: Vax Floating Point
Chapter 40. VAX Dependent Features option determines how we map names. This takes several values. No switch at all allows case hacking as described above. A value of zero ( ) implies names should be upper case, and inhibits the case hack. A value of 2 ( ) implies names should be all lower case, with no case hack.
Page 241: Vax Opcodes
Chapter 40. VAX Dependent Features .gfloat This expects zero or more ﬂonums, separated by commas, and assembles Vax format 64-bit ﬂoating point constants. .hfloat This expects zero or more ﬂonums, separated by commas, and assembles Vax format 128-bit ﬂoating point constants. 40.4.
Page 242 Chapter 40. VAX Dependent Features COND may be any one of the conditional branches COND nequ eqlu gtru may also be one of the bit tests lequ gequ lssu COND is the opposite condition to bssi bcci NOTCOND COND (byte displacement) COND (word displacement) foo ;...
Page 243: Vax Operands
Chapter 40. VAX Dependent Features (long displacement) ..., foo ; OPCODE brb bar ; foo: jmp destination bar: aobleq aoblss sobgeq sobgtr (byte displacement) OPCODE (word displacement) ..., foo ; OPCODE brb bar ; foo: brw destination bar: (long displacement) ..., foo ;...
Page 244 Chapter 40. VAX Dependent Features 40.7. Not Supported on VAX Vax bit ﬁelds can not be assembled with . Someone can add the required code if they really need it.
Page 245: V850 Dependent Features
Chapter 41. v850 Dependent Features 41.1. Options supports the following additional command-line options for the V850 processor family: -wsigned_overflow Causes warnings to be produced when signed immediate values overﬂow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.
Page 246: Syntax
Chapter 41. v850 Dependent Features 41.2. Syntax 41.2.1. Special Characters is the line comment character. 41.2.2. Register Names supports the following names for registers: general register 0 r0, zero general register 1 general register 2 r2, hp general register 3 r3, sp general register 4 r4, gp...
Page 247 Chapter 41. v850 Dependent Features general register 13 general register 14 general register 15 general register 16 general register 17 general register 18 general register 19 general register 20 general register 21 general register 22 general register 23 general register 24 general register 25 general register 26 general register 27...
Page 248: Floating Point
Chapter 41. v850 Dependent Features general register 30 r30, ep general register 31 r31, lp system register 0 eipc system register 1 eipsw system register 2 fepc system register 3 fepsw system register 4 system register 5 system register 16 ctpc system register 17 ctpsw...
Page 249: Opcodes
Chapter 41. v850 Dependent Features .offset expression & Moves the offset into the current section to the speciﬁed amount. .section "name", type This is an extension to the standard .section directive. It sets the current section to be type and creates an alias for this section called "name". .v850 Speciﬁes that the assembled code should be marked as being targeted at the V850 processor.
Page 250 Chapter 41. v850 Dependent Features movhi hi(here), r0, r6 movea lo(here), r6, r6 The reason for this special behaviour is that movea performs a sign extension on its immedi- ate operand. So for example if the address of ’here’ was 0xFFFFFFFF then without the spe- cial behaviour of the hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the movea instruction would takes its immediate operand, 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF which is wrong (the ﬁfth nibble is E).
Page 251 Chapter 41. v850 Dependent Features ctoff() Computes the offset of the named variable from the start of the Call Table Area (whoes address is helg in system register 20, the CTBP register) and stores the result a 6 or 16 bit unsigned value in the immediate ﬁeld of then given instruction or piece of data.
Page 252 Chapter 41. v850 Dependent Features...
Page 253: Xtensa Dependent Features
Chapter 42. Xtensa Dependent Features This chapter covers features of the gnu assembler that are speciﬁc to the Xtensa architecture. For details about the Xtensa instruction set, please consult the [Xtensa Instruction Set Architecture (ISA) Reference Manual]. 42.1. Command Line Options The Xtensa version of the gnu assembler supports these special options: -density | -no-density Enable or disable use of the Xtensa code density option (16-bit instructions).
Page 254: Assembler Syntax
Chapter 42. Xtensa Dependent Features 42.2. Assembler Syntax Block comments are delimited by . End of line comments may be introduced with either Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands: ,...] opcode operand...
Page 255: Automatic Instruction Alignment
Chapter 42. Xtensa Dependent Features 42.3.1. Using Density Instructions The Xtensa instruction set has a code density option that provides 16-bit versions of some of the most commonly used opcodes. Use of these opcodes can signiﬁcantly reduce code size. When pos- sible, the assembler automatically translates generic instructions from the core Xtensa instruction set into equivalent instructions from the Xtensa code density option.
Page 256: Function Call Relaxation
Chapter 42. Xtensa Dependent Features bnez.n a2, M (The instruction would be used in this example only if the density option is available. Other- BNEZ.N wise, would be used.) BNEZ 42.4.2. Function Call Relaxation Function calls may require relaxation because the Xtensa immediate call instructions ( CALL0 CALL4 ) provide a PC-relative offset of only 512 Kbytes in either direction.
Page 257: Directives
Chapter 42. Xtensa Dependent Features machine instruction can only be used with immediate offsets in the range from 0 to 255. L8UI machine instructions can only be used with offsets from 0 to 510. The L16SI L16UI L32I machine instruction can only be used with offsets from 0 to 1020. A load offset outside these ranges can be materalized with an instruction if the destination register of the load is different than the L32R...
Page 258: Density
Chapter 42. Xtensa Dependent Features All the Xtensa-speciﬁc directives that apply to a region of code use this syntax. The directive applies to code between the and the . The state of the option after the .begin .end .end reverts to what it was before the .
Page 259: Longcalls
Chapter 42. Xtensa Dependent Features Relaxation is enabled by default unless the command-line option was speciﬁed. -no-relax 42.5.3. longcalls directive enables or disables function call relaxation. Section 42.4.2 Function Call longcalls Relaxation. .begin [no-]longcalls .end [no-]longcalls Call relaxation is disabled by default unless the command-line option is speciﬁed.
Page 260: Literal_Position
Chapter 42. Xtensa Dependent Features there are no preceding instructions or directives, the assembler will ENTRY .literal_position print a warning and place the literal pool at the beginning of the current section. In such cases, explicit directives should be used to place the literal pools. .literal_position 42.5.6.
Page 261: Freeregs
Chapter 42. Xtensa Dependent Features 42.5.8. freeregs This directive tells the assembler that the given registers are unused in the region. .begin freeregs ...] .end freeregs This allows the assembler to use these registers for relaxations or optimizations. (They are actually only for relaxations at present, but the possibility of optimizations exists in the future.) Nested directives can be used to add additional registers to the list of those available to the...
Page 262 Chapter 42. Xtensa Dependent Features...
Page 263: Reporting Bugs
Chapter 43. Reporting Bugs Your bug reports play an essential role in making reliable. Reporting a bug may help you by bringing a solution to your problem, or it may not. But in any case the principal function of a bug report is to help the entire community by making the next version of work better.
Page 264 Chapter 43. Reporting Bugs The version of announces it if you start it with the argument. • -version Without this, we will not know whether there is any point in looking for the bug in the current version of Any patches you may have applied to the source.
Page 265 Chapter 43. Reporting Bugs A patch for the bug does help us if it is a good one. But do not omit the necessary information, such as the test case, on the assumption that a patch is all we need. We might see problems with your patch and decide to ﬁx the problem another way, or we might not understand it at all.
Page 266 Chapter 43. Reporting Bugs...
Page 267: Acknowledgements
Chapter 44. Acknowledgements If you have contributed to and your name isn’t listed here, it is not meant as a slight. We just don’t know about it. Send mail to the maintainer, and we’ll correct the situation. Currently the maintainer is Ken Raeburn (email address raeburn@cygnus.com Dean Elsner wrote the original gnu assembler for the VAX.
Page 268 Chapter 44. Acknowledgements Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF object formats). This work was supported by both the Center for Software Science at the University of Utah and Cygnus Support. Support for ELF format ﬁles has been worked on by Mark Eichin of Cygnus Support (original, in- complete implementation for SPARC), Pete Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn...
Page 269: Gnu Free Documentation License
Appendix A. GNU Free Documentation License Version 1.1, March 2000 Copyright (C) 2000, Free Software Foundation, Inc. 59 Temple Place, Suite 330, Boston, MA 02111-1307 Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. 1.
Page 270 Appendix A. GNU Free Documentation License A "Transparent" copy of the Document means a machine-readable copy, represented in a for- mat whose speciﬁcation is available to the general public, whose contents can be viewed and edited directly and straightforwardly with generic text editors or (for images composed of pix- els) generic paint programs or (for drawings) some widely available drawing editor, and that is suitable for input to text formatters or for automatic translation to a variety of formats suit- able for input to text formatters.
Page 271 Appendix A. GNU Free Documentation License version of the Document. 5. MODIFICATIONS You may copy and distribute a Modiﬁed Version of the Document under the conditions of sec- tions 2 and 3 above, provided that you release the Modiﬁed Version under precisely this License, with the Modiﬁed Version ﬁlling the role of the Document, thus licensing distribution and mod- iﬁcation of the Modiﬁed Version to whoever possesses a copy of it.
Page 272 Appendix A. GNU Free Documentation License You may combine the Document with other documents released under this License, under the terms deﬁned in section 4 above for modiﬁed versions, provided that you include in the combi- nation all of the Invariant Sections of all of the original documents, unmodiﬁed, and list them all as Invariant Sections of your combined work in its license notice.
Page 273: Addendum: How To Use This License For Your Documents
Appendix A. GNU Free Documentation License The Free Software Foundation may publish new, revised versions of the GNU Free Documenta- tion License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. See http://www.gnu.org/copyleft/. Each version of the License is given a distinguishing version number.
Page 274 Appendix A. GNU Free Documentation License...
Page 275 Index subsym builtin, TIC54X, see Section 38.10 $isname Macros subsym builtin, TIC54X, see Section 38.10 $isreg Macros #, see Section 4.3 Comments subsym builtin, TIC54X, see Section 38.10 $lastch #APP, see Section 4.1 Preprocessing Macros #NO_APP, see Section 4.1 Preprocessing math builtin, TIC54X, see Section 38.7 Math $ldexp in symbol names, see Section 36.2.1 Special Char-...
Page 276 Index options, i960, see Section 23.1 i960 Command-line command line option, CRIS, -emulation=criself Options see Section 14.1 Command-line Options -enforce-aligned-data, see Section 37.2 Enforcing -ac, see Section 3.1 Enable Listings: -a[cdhlns] aligned data -ad, see Section 3.1 Enable Listings: -a[cdhlns] -f, see Section 3.4 Work Faster: -ah, see Section 3.1 Enable Listings: -a[cdhlns]...
Page 277 Index -longcalls, see Section 42.1 Command Line Options command line option, Alpha, see Section 11.2 -M, see Section 3.9 Assemble in MRI Compatibility Options Mode: option, cpu, see Section 38.1 Options -mcpu -m11/03, see Section 32.1 Options command line option, ARM, see Section 13.1 -mcpu= Options -m11/04, see Section 32.1 Options...
Page 278 Index -mno-fp-11, see Section 32.1 Options command line option, MMIX, -no-merge-gregs see Section 30.1 Command-line Options -mno-fpp, see Section 32.1 Options command line option, CRIS, -mno-fpu, see Section 32.1 Options -no-mul-bug-abort see Section 14.1 Command-line Options -mno-kev11, see Section 32.1 Options option, M32RX, see Section 25.1 -mno-limited-eis, see Section 32.1 Options -no-parallel...
Page 279 Index -statistics, see Section 3.13 Display Assembly Statis- directive, M32R2, see Section 25.2 M32R Di- .m32r2 tics: rectives -statistics directive, M32RX, see Section 25.2 M32R Section 27.1 .m32rx -strict-direct-mode Directives M68HC11 and M68HC12 Options .o, see Section 2.6 Output (Object) File , ignored on VAX, see Section 40.1 VAX Command- on HPPA, see Section 19.5 HPPA Assembler Line Options...
Page 280 Index (doublequote character), see Section 4.6.1.1 directive, see Section 8.3 \" align .align abs-expr Strings abs-expr abs-expr character), see Section 4.6.1.1 Strings directive, ARM, see Section 13.4 ARM Ma- align (backspace character), see Section 4.6.1.1 Strings chine Directives (octal character code), see Section 4.6.1.1 directive, M88K, see Section 28.1 M88K Ma- align Strings...
Page 281 Index ARC machine directives, see Section 12.4 ARC Ma- ARM opcodes, see Section 13.5 Opcodes chine Directives ARM options (none), see Section 13.1 Options ARC opcodes, see Section 12.5 Opcodes ARM register names, see Section 13.2.2 Register ARC options (none), see Section 12.1 Options Names ARC register names, see Section 12.2.2 Register ARM support, see Chapter 13 ARM Dependent Fea-...
Page 282 Index assembler directives, M68HC12, see Section 27.4 As- branch improvement, M680x0, see Section 26.6.1 sembler Directives Branch Improvement assembler directives, MMIX, see Section 30.3.4 As- branch improvement, M68HC11, see Section 27.6.1 sembler Directives Branch Improvement assembler internal logic error, see Section 5.3 Assem- branch improvement, VAX, see Section 40.5 VAX bler Internal Sections Branch Improvement...
Page 283 Index directive, Section compare/branch instructions, i960, see Section 23.4.2 cfi_startproc Compare-and-Branch .cfi_startproc directive, TIC54X, see Section 38.9 Directives comparison expressions, see Section 7.2.4 Inﬁx Oper- char character constants, see Section 4.6.1 Character Con- ators stants conditional assembly, see Section 8.45 absolute character escape codes, see Section 4.6.1.1 Strings expression...
Page 284 Index CRIS line comment characters, see Section 14.3.1 D30V Guarded Execution, see Section 16.2.4 Special Characters Guarded Execution CRIS options, see Section 14.1 Command-line Op- D30V line comment character, see Section 16.2.3 Spe- tions cial Characters CRIS position-independent code, see Section 14.1 D30V nops, see Chapter 2 Overview Command-line Options D30V nops after 32-bit multiply, see Chapter 2...
Page 285 Index directive, see Section 8.21 desc .desc symbol abs-expression ECOFF sections, see Section 29.2 MIPS ECOFF ob- descriptor, of symbol, see Section 6.5.3.1 De- a.out ject code scriptor register, V850, see Section 41.2.2 Register Names directive, M88K, see Section 28.1 M88K Ma- dfloat eight-byte integer, see Section 8.74 .quad...
Page 286 Index ESA/390 ﬂoating point (ieee), see Section 20.4 Float- register, V850, see Section 41.2.2 Register fepsw ing Point Names ESA/390 support, see Chapter 20 ESA/390 Dependent directive, M88K, see Section 28.1 M88K Ma- ffloat Features chine Directives ESA/390 Syntax, see Section 20.2 Options directive, VAX, see Section 40.3 Vax Ma- ffloat chine Directives...
Page 287 Index ﬂoating point, i386, see Section 21.8 Floating Point ﬂoating point, i960 (ieee), see Section 23.2 Floating H8/300 addressing modes, see Section 17.2.3 Ad- Point dressing Modes ﬂoating point, M680x0, see Section 26.4 Floating H8/300 ﬂoating point (ieee), see Section 17.3 Float- Point ing Point ﬂoating point, M68HC11, see Section 27.5 Floating...
Page 288 Index HPPA ﬂoating point (ieee), see Section 19.4 Floating i860 machine directives, see Section 22.3 i860 Ma- Point chine Directives i860 opcodes, see Section 22.4 i860 Opcodes HPPA Syntax, see Section 19.2 Options i860 support, see Chapter 22 Intel i860 Dependent HPPA-only directives, see Section 19.5 HPPA Assem- Features bler Directives...
Page 289 Index directive, see Section 8.45 directive, H8/500, see Section 18.4 H8/500 Ma- ifnotdef absolute chine Directives expression immediate character, ARM, see Section 13.2.1 Spe- directive, i386, see Section 21.8 Floating Point cial Characters directive, TIC54X, see Section 38.9 Directives immediate character, M680x0, see Section 26.6.2 Spe- directive, x86-64, see Section 21.8 Floating Point cial Characters integer expressions, see Section 7.2 Integer Expres-...
Page 290 Index jump/call operands, x86-64, see Section 21.2 AT&T line comment character, SH64, see Section 36.2.1 Syntax versus Intel Syntax Special Characters instructions, relaxation, see Section 42.4.3 line comment character, V850, see Section 41.2.1 L16SI Other Immediate Field Relaxation Special Characters instructions, relaxation, see Section 42.4.3 line comment character, Z8000, see Section 39.2.1 L16UI...
Page 291 Index directive, see Section 42.5.7 lit- M680x0 branch improvement, see Section 26.6.1 literal_prefix eral_preﬁx Branch Improvement little endian output, MIPS, see Chapter 2 Overview M680x0 directives, see Section 26.5 680x0 Machine Directives little endian output, PJ, see Chapter 2 Overview M680x0 ﬂoating point, see Section 26.4 Floating little-endian output, MIPS, see Section 29.1 Assem- Point...
Page 292 Index machine directives, ARM, see Section 13.4 ARM Ma- MIPS architecture options, see Section 29.1 Assem- chine Directives bler options machine directives, H8/300 (none), see Section 17.4 MIPS big-endian output, see Section 29.1 Assembler H8/300 Machine Directives options machine directives, H8/500 (none), see Section 18.4 MIPS debugging directives, see Section 29.3 Direc- H8/500 Machine Directives tives for debugging information...
Page 293 Index MMIX pseudo-op BSPEC, see Section 30.3.4 Assem- MRI compatibility mode, see Section 3.9 Assemble in bler Directives MRI Compatibility Mode: MMIX pseudo-op BYTE, see Section 30.3.4 Assem- directive, see Section 8.57 .mri bler Directives MRI mode, temporarily, see Section 8.57 .mri MMIX pseudo-op ESPEC, see Section 30.3.4 Assem- MSP 430 ﬂoating point (ieee), see Section 31.3 Float-...
Page 294 Index number of macros executed, see Section 8.60 optimization, D10V, see Chapter 2 Overview .macro optimization, D30V, see Chapter 2 Overview numbered subsections, see Section 5.4 Sub-Sections optimizations, see Section 42.3 Xtensa Optimizations numbers, 16-bit, Section 8.43 .hword directive, ARC, see Section 12.4 ARC Ma- option expressions numeric values, see Chapter 7 Expressions...
Page 295 Index preﬁxes, i386, see Section 21.5 Instruction Preﬁxes preprocessing, see Section 4.1 Preprocessing padding the location counter, see Section 8.3 .align preprocessing, turning on and off, see Section 4.1 Pre- abs-expr abs-expr abs-expr processing padding the location counter given a power of directive, see Section 8.67 previous .previous...
Page 296 Index directive, see Section 8.71 registers, x86-64, see Section 21.4 Register Naming psize .psize lines columns registers, Z8000, see Section 39.2.2 Register Names directive, TIC54X, see Section 38.9 Direc- pstring directive, see Section 42.5.2 relax relax tives relaxation, see Section 42.4 Xtensa Relaxation register, V850, see Section 41.2.2 Register Names relaxation of instructions, see Section 42.4.3...
Page 297 Index SH support, see Chapter 35 Renesas / SuperH SH De- pendent Features search path for , see Section 3.5 .include SH64 ABI options, see Section 36.1 Options Search Path: .include -Ipath SH64 addressing modes, see Section 36.2.3 Address- directive, AMD 29K, see Section 10.4 AMD sect ing Modes 29K Machine Directives...
Page 298 Index directive, M680x0, see Section 26.5 680x0 Ma- standard input, as input ﬁle, see Section 2.4 Command skip chine Directives Line statement separator character, see Section 4.5 State- directive, SPARC, see Section 37.4 Sparc Ma- skip ments chine Directives statement separator, Alpha, see Section 11.3.1 Special directive, see Section 8.83 sleb128 .sleb128...
Page 299 Index support, see Chapter 19 HPPA Dependent Features symbols, local common, see Section 8.52 .lcomm supporting ﬁles, including, see Section 8.47 symbol length directive, see Section 8.90 .include " " symver .symver file suppressing warnings, see Section 3.16 Control Warn- syntax compatibility, i386, see Section 21.2 AT&T ings: Syntax versus Intel Syntax...
Page 300 Index time, total for assembly, see Section 3.13 Display As- value attribute, COFF, see Section 8.96 .val addr sembly Statistics: -statistics value of a symbol, see Section 6.5.1 Value directive, Section 8.93 title .title directive, TIC54X, see Section 38.9 Directives "...
Page 301 Index x86-64 att_syntax pseudo op, see Section 21.2 AT&T Syntax versus Intel Syntax warning for altered difference tables, see Section 3.6 x86-64 conversion instructions, see Section 21.3 In- Difference Tables: struction Naming warning messages, see Section 2.7 Error and Warning x86-64 ﬂoating point, see Section 21.8 Floating Point Messages warnings,...
Page 302 Index Z800 addressing modes, see Section 39.2.3 Address- ing Modes Z8000 directives, see Section 39.3 Assembler Direc- tives for the Z8000 Z8000 line comment character, see Section 39.2.1 Special Characters Z8000 line separator, see Section 39.2.1 Special Char- acters Z8000 opcode summary, see Section 39.4 Opcodes Z8000 options, see Section 39.1 Options Z8000 registers, see Section 39.2.2 Register Names Z8000 support, see Chapter 39 Z8000 Dependent Fea-...

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Enterprise linux 4

Red Hat ENTERPRISE LINUX 4 - USING AS Using Manual

1 Using as

2 Overview

3 Command-Line Options

4 Syntax

5 Sections and Relocation

6 Symbols

7 Expressions

8 Assembler Directives

9 Machine Dependent Features

10 AMD 29K Dependent Features

11 Alpha Dependent Features

12 ARC Dependent Features

13 ARM Dependent Features

14 CRIS Dependent Features

15 D10V Dependent Features

16 D30V Dependent Features

17 H8/300 Dependent Features

18 H8/500 Dependent Features

19 HPPA Dependent Features

20 ESA/390 Dependent Features

21 Dependent Features

22 Intel I860 Dependent Features

23 Intel 80960 Dependent Features

24 IP2K Dependent Features

25 M32R Dependent Features

26 M680X0 Dependent Features

27 M68HC11 and M68HC12 Dependent Features

28 Motorola M88K Dependent Features

29 MIPS Dependent Features

2009 MMIX Dependent Features

31 MSP 430 Dependent Features

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