Sony CFD-E100WHITE Service Manual page 44

CFD-E100/E100L
Pin No. Pin Name
71 XT2
72
VDD
73
VSS
74 X1
75
X2
76
RST
77 V-CLK
78 V-DATA
79 SCL
80
SDA
44
I/O
O
Sub system clock output terminal (32.768 kHz)
- Power supply terminal (+3.3V)
- Ground terminal
I Main system clock input terminal (4.19 MHz)
O Main system clock output terminal (4.19 MHz)
System reset signal input "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
O
Serial data transfer clock signal output to the electrical volume
O Serial data output to the electrical volume
O
Serial data transfer clock signal output to EEPROM
I/O Two-way data bus with the EEPROM
Description