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ARMADA 88F6828
Hardware design manual
Marvell ARMADA 88F6828 Hardware Design Manual
38x family high-performance sing
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Contents
Table of Contents
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Table of Contents
Table of Contents
Revision History
Introduction
Table 1: Revision History
Table 1: Related Documents
4-Layer Board Recommendations
Stack-Up Example
Table 2: 4-Layer Stack up Example
General Guidelines
88F6810, 88F6820 and 88F6828 Power Filtering
Routing Guidelines for the ISET Signal
Board Recommendations for Stripline Routing PCB
Table 3: List of Capacitors
Generic Guidelines for SERDES Interfaces
Insertion Loss and Loss Budget
Figure 1: Insertion Loss Curve
Inter-Symbol Interference (ISI)
Figure 2: Typical Trace Differential Amplitude Insertion Loss and ISI
Figure 3: Difference in Attenuation Due to ISI - Time Domain Influence
Figure 4: ISI Originated Jitter - Eye Pattern
Placement of Devices and Connectors on the Board
PCB Materials Selection
Crosstalk
Figure 5: Stack-Up Cross-Section with a High Probability of Crosstalk
Return Path Continuity
Figure 6: Non-Continuous Reference Plane Return Current Path Influence
Figure 7: Layer Transfer
Target Routing Impedance
Figure 8: Reference Plane Clearance
Figure 9: Changed Width for Differential Impedance Compensation
Capacitive Discontinuities
Figure 10: Voids Underneath AC Coupling Capacitors' Pads
Figure 11: Voids Underneath BGA Device Ball
Figure 12: Voids Underneath SMT Connector/Qfp Lead Frame Pads
Trace Symmetry and Matching-Mode Conversion
Via Structures
Figure 13: Proper Deskew
Figure 14: Via Structures
Figure 15: Via Stubs
Figure 16: Differential Via Structure
Figure 17: Recommended Via Structure Dimensions for SERDES Interface up to 12.5 Gbps
Selecting the Appropriate Components
Figure 18: Recommended Via Structure Dimensions for 25 Gbps SERDES Interfaces
Generic Power Board Guidelines
Generic Power Network Guidelines
DC Voltage Drop
Polygon Shape Considerations
Figure 19: Coupling of Vias
Figure 20: Routing Length between the Capacitor and the Vias
Analog Power Filtering
Figure 21: Required Analog Power Filter Voltage Transfer Function
Figure 22: Analog Power Filter Example
Table 4: Definition of Analog Power Filter Symbols
Core Power Decoupling
I/O Power Bypassing
Bulk Capacitors
Figure 23: Return Path Discontinuity-Bypass Capacitor
Figure 24: Placement of a Bypass Capacitor in Relation to Device Ground Pins
Termination Voltage (VTT) Layout Recommendations
Unused Interface
JTAG Connection Information
Figure 25: JTAG Connection
16-Bit SDRAM DDR3 Interface
Interface Connectivity
Table 5: Signal Groups
Figure 26: on Board 1X16-Bit Wide Memory Device with ECC Connected to the Controller
Figure 27: on Board 2X8-Bit Wide Memory Devices with ECC Connected to the Controller
Figure 28: on Board 16-Bit, 4X8-Bit Wide Memory Devices with ECC Connected to the Controller
Interface Signals Layout Guidelines
Figure 29: on Board 16-Bit, 1X16-Bit Wide Memory with ECC Topology-Address and Control
Figure 30: on Board 16-Bit, 1X16-Bit Single-Side Assembly Topology with ECC-Data
Table 6: Routing Constraints When Using on Board 16-Bit, 1X16-Bit Wide Memory Topology
Figure 31: on Board 16-Bit, 2X8-Bit Wide Memory Topology with ECC -Address
Figure 32: On-Board 16-Bit, 2X8-Bit with ECC, Single-Side Assembly Topology-Data
Table 7: Routing Constraints-On-Board 16-Bit, 2X8-Bit Topology
Figure 33: on Board 16-Bit, 4X8-Bit Wide Memory Topology for Clock/Address/Command/Control with
Figure 34: on Board 16-Bit, 4X8-Bit Wide Memory with ECC Topology for Data
Table 8: Routing Constraints When Using on Board 16-Bit, 4X8-Bit Wide Memory Topology Using a
Special Software Setting
Table 9: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select
Table 10: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly
32-Bit SDRAM DDR3 Interface
Interface Connectivity
Table 11: Signal Groups
Figure 35: On-Board 32-Bit 2 Memory Devices, 2X16-Bit Single-Side Connectivity
Figure 36: On-Board 32-Bit, 4X8-Bit Single-Side Connectivity
Figure 37: On-Board 32-Bit, 8X8-Bit Clamshell Connectivity with ECC
Interface Signals Layout Guidelines
Figure 38: On-Board 32-Bit, 2X16-Bit Single-Side Assembly Topology-Address and Control with ECC
Figure 39: On-Board 32-Bit, 2X16-Bit Single-Side Assembly Topology with ECC-Data
Table 12: Routing Constraints-32-Bit, 2X16-Bit Single Side Assembly Topology
Figure 40: On-Board 32-Bit, 4X8-Bit Single-Side Assembly Topology with ECC-Address and Control
Figure 41: On-Board 32-Bit, 4X8-Bit, with ECC, Single-Side Assembly Topology-Data
Table 13: Routing Constraints-On-Board 32-Bit with or Without ECC, 4X8-Bit Topology
Figure 42: On-Board 32-Bit, 8X8-Bit Clamshell Topology with ECC-Address and Control
Figure 43: On-Board 32-Bit, 8X8-Bit Clamshell Topology with ECC-Data
Table 14: Routing Constraints-On-Board 32-Bit with or Without ECC, 8X8-Bit Clamshell Topology
Power Signals
Special Software Setting
Table 15: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select
Table 16: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly
32-Bit SDRAM DDR4 Interface
Interface Connectivity
Figure 44: On-Board 32-Bit, 4X8-Bit Single-Side Connectivity
Interface Signals Layout Guidelines
Figure 45: On-Board 32-Bit, 4X8-Bit Single-Side Assembly Topology with ECC-Address and Control
Figure 46: On-Board 32-Bit, 4X8-Bit, with ECC, Single-Side Assembly Topology-Data
Table 18: Routing Constraints-On-Board 32-Bit with or Without ECC, 4X8-Bit Topology
Power Signals
Special Software Setting
Table 19: ODT Control Matrix for SDRAM DDR4 with 1 Chip Select
Network Ethernet Ports
Reduced Gigabit Media Independent Interface (RGMII)
Interface Connectivity
Connectivity
Interface Signals Layout Guidelines
Figure 47: RGMII Port Connection to PHY
Figure 48: RGMII Port Connection to Another RGMII MAC
Figure 49: RGMII Routing Topology
Table 21: no Internal Delay on Transmitting or on Receiving Peer Side-Tx Path
Table 22: Internal Delay on Transmitting or on Receiving Peer Side-Tx Path
Table 23: no Internal Delay on Receiving or on Transmitting Peer Side-Rx Path
Table 24: Internal Delay on Receiving or on Transmitting Peer Side-Rx Path
Serial Gigabit Media Independent Interface (SGMII)
Interface Connectivity
Figure 50: SGMII Generic Point-To-Point Connection
Table 17: Signal Groups
Interface Signals Layout Guidelines for Chip-To-Chip End-To-End Connection
Figure 51: SGMII Topology for Chip-To-Chip, End-To-End Connection
Table 26: Routing Constraints Chip-To-Chip, End-To-End Connection
Power Considerations
Specific Signals
High Speed Serial Gigabit Media Independent Interface (HS-SGMII)
Interface Connectivity
Figure 52: SGMII Generic Point-To-Point Connection
Table 20: Signal Groups
Interface Signals Layout Guidelines
Figure 53: Topology for Chip-To-Chip, End-To-End Connection
Table 28: Routing Constraints for a Chip-To-Chip End-To-End Connection
Power Considerations
Specific Signals
Quad Serial Gigabit Media Independent Interface (QSGMII)
Interface Connectivity
Figure 54: QSGMII Generic Point-To-Point Connection
Table 29: Signal Groups
Interface Signals Layout Guidelines for Chip-To-Chip End-To-End Connection
Figure 55: QSGMII Topology for Chip-To-Chip, End-To-End Connection
Table 30: Routing Constraints for a Chip-To-Chip End-To-End Connection Topology
Clock Considerations
Power Considerations
Specific Signals
PCI Express (Pcie) Interface 1.0/1.1
Connectivity
Table 31: Signal Groups
Table 32: Specific Device
Figure 56: PCI Express Interface Connectivity
Device
Interface Signals Layout Guidelines
Figure 58: Topology with an Existing Connector And/Or an Add-In Card
Table 33: System Board with Existing Connector
Table 34: Add-In Card
Figure 59: Topology with a Same-Board Connection
Table 35: Same-Board Connection
Power Considerations
Specific Signals
PCI Express (Pcie) Interface 2.0
Connectivity
Table 36: Signal Groups
Table 37: Specific Device
Figure 60: PCI Express Interface Connectivity
Interface Signals Layout Guidelines
Figure 61: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell ® Device
Figure 62: Topology with an Existing Connector And/Or an Add-In Card
Table 38: System Board with Existing Connector
Table 39: Add-In Card
Figure 63: Topology with a Same-Board Connection
Table 40: Same-Board Connection
Power Considerations
Reference Clock Considerations
Specific Signals
Universal Serial Bus (USB) 2.0 Interface
Interface Connectivity
Figure 64: USB 2.0 Interface Connectivity to a Connector-Including Optional Common Mode Choke and Protection Diodes Circuitry
Table 25: Signal Groups
Table 27: Signal Groups
Table 41: USB Interface Pin Connectivity Groups
Figure 65: Vbus Connectivity When Configured as a Host
Figure 66: Vbus Connectivity When Configured as a Device
Interface Signals Layout Guidelines
Figure 67: Topology-Including Common Mode Choke and Protection Diodes Optional Circuitry-When Configured as a Device
Table 42: Routing Constraints When Configured as a Device
Figure 68: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry-When Configured as a Host
Table 43: Routing Constraints When Configured as a Host
Power Considerations
Specific Signals
Universal Serial Bus (USB) 3.0 Interface
General Design Considerations
Interface Connectivity
Table 44: USB Interface Pin Connectivity Groups
Figure 69: Topology-Including Common Mode Choke and Protection Diodes Optional Circuitry-When Configured as a Device
Table 45: Routing Constraints When Configured as a Device
Figure 70: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry-When Configured as a Host
Table 46: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry- When Configured as a Host
Serial ATA (SATA) Interface 3.0
Connectivity
Interface Signals Layout Guidelines
Figure 71: SATA Interface Connectivity
Table 47: Signal Groups
Figure 72: Topology for Connection to a Standard SATA 3.0 1-Meter Cable
Table 48: Connection to a Standard SATA 3.0 1-Meter Cable
Clock Considerations
Power Considerations
Specific Signals
SDIO 3.0 and MMC 4.4
Interface Connectivity
Connectivity
Figure 73: SDIO 3.0/MMC4.4 Connection to Connector Side
Table 49: Signal Groups
Figure 74: SDIO 3.0/MMC 4.4 Routing Topology
Table 50: Routing Constraints for SDIO 3.0 and MMC 4.4 Interfaces
Serial Management Interface (SMI)
Interface Connectivity
Interface Signals Layout Guidelines
Figure 75: Clock Transition Examples
Figure 76: Master SMI Connectivity Example
Device Bus Interface
Device Bus Interface Connectivity
Figure 77: Using Two 8-Bit Flash Devices to Comprise a 16-Bit Bus
Figure 78: Example of a 16-Bit Wide Device Connection
Figure 79: Example of a 512 KB Flash Device with an 8-Bit Data Bus Connection
Dev_Readyn Support
Device Bus Interface Control Signals at Reset
Figure 80: Dev_Readyn Connection Example
NAND Flash Support
Figure 81: Connectivity for Chip Enable Don't Care NAND Flash
General Clock Guidelines
Core Clock
Figure 82: Core Clock Connectivity
Table 51: Core Clock Tx/Rx Path Constraints
Figure 83: Reference Clock Distribution
ARMADA ® 38X Family Clock Topology
Clock Topology
Figure 84: Clock Topology
PCI Express Clock Topology
Figure 85: Internal Reference Clock with up to 2 Pcie Root Complex Ports
Figure 86: External Reference Clock with 4 Pcie Root Complex Ports
Figure 87: External Reference Clock with 1 Pcie Endpoint and 3 Root Complex Ports
Figure 88: Internal Reference Clock Topology with 4 Pcie Root Complex Ports
Figure 89: Internal Reference Clock Topology with 1 Pcie Endpoint and 3 Root Complex Ports
Adaptive Voltage Scaling (AVS)
Connectivity
Figure 90: Board Connectivity for VDD_CPU with Direct AVS Feedback Connection
Figure 91: Board Connectivity for VDD_CPU with AVS Feedback Connection with Resistor Voltage
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Table of Contents
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Introduction
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88F6810, 88F6820 and 88F6828 Power Filtering
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88F6810, 88F6820 and
88F6828
®
ARMADA
38x Family
High-Performance Single/Dual Core
CPU System on Chip
Hardware Design Guide
Marvell.
Moving Forward Faster
Doc. No. MV-S302310-U0, Rev. A
August 30, 2017
Document Classification: Public
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