Dram Timing Configuration; Memory Configuration - Biostar TA870 - BIOS Manual

TA870 BIOS Manual

DRAM Timing Configuration

DRAM Timing Configuration
Memory CLK
CAS Latency(Tcl)
RAS/CAS Delay(Trcd)
Row Precharge Time(Trp):
Min Active RAS(Tras)
RAS/RAS Delay(Trrd)
Row Cycle (Trc)
Command Rate(CR)
Write Recover Time(Twr):
> Memory Configuration
> ECC Configuration
> BIOSTAR Memory Insight
Memory Clock Mode
Memclock Value
DRAM Timing Mode
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.

Memory Configuration

Memory Configuration
Bank Interleaving
Channel Interleaving
MemClk Tristate C3/ATLVID
Memory Hole Remapping
DCT Unganged Mode
Power Down Enable
Page Smashing
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
perform ance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options: Auto (Default)
BIOS SETUP UTILITY
:
:
:
:
:
:
:
[Auto]
[DDR3-800]
[Auto]
BIOS SETUP UTILITY
[Auto]
[XOR of Address bit]
[Disabled]
[Enabled]
[Always]
[Disabled]
[Disabled]
33
T-Series
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
T-Series
Enable Bank Memory
Interleaving
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit