Related Manuals for MIPS MIPS32 74Kc
Summarization of Contents
Introduction
Intended Audience
Identifies the target readers for this manual, assuming familiarity with MIPS architecture.
Conventions
Explains formatting, mnemonics, and register naming conventions used throughout the manual.
74K™ core features
Details the optional features and configurations available for the 74K family cores.
A brief guide to the 74K™ core implementation
Provides an overview of the 74K core's long pipeline, out-of-order execution, and branch handling.
Initialization and identity
Probing your CPU - Config CP0 registers
Describes how to use CP0 Config registers to determine CPU capabilities and features.
PRId register — identifying your CPU type
Explains the PRId register for identifying the specific CPU core and its revision.
Memory map, caching, reads, writes and translation
The memory map
Details the system's memory map, including virtual and physical address ranges.
Reads, writes and synchronization
Explains memory access ordering, non-blocking loads, and synchronization mechanisms.
Caches
Covers the L1 and L2 caches, their configurations, and management operations.
The TLB and translation
Describes the Translation Lookaside Buffer (TLB) for virtual to physical address translation.
Bus error exception
Details how bus errors are signaled and handled, typically indicating system failures.
Scratchpad memory/SPRAM
Explains the use of on-chip scratchpad RAM for high-speed data access.
Programming the 74K™ core in user mode
User-mode accessible “Hardware registers”
Describes registers accessible from user mode for hardware status and control.
Tuning software for the 74K‘ family pipeline
Provides guidance for optimizing software performance by understanding the pipeline.
Data dependency delays
Details instruction dependencies and their impact on pipeline execution timing.
Kernel-mode (OS) programming and Release 2 of the MIPS32® Architecture
Hazard barrier instructions
Explains instructions used to manage pipeline hazards and ensure correct execution order.
MIPS32® Architecture Release 2 - enhanced interrupt system(s)
Covers new interrupt features like VI and EIC modes introduced in Release 2.
Exception Entry Points
Details how exceptions are handled and entry points are managed.
Shadow registers
Describes shadow register sets for efficient interrupt handler context switching.
The HWREna register - Control user rdhwr access
Explains how to control user-mode access to hardware registers via rdhwr.
Floating point unit
Data representation
Describes the formats for 32-bit and 64-bit floating-point numbers.
Basic instruction set
Provides an overview of the FPU's instruction set and data type suffixes.
Setting up the FPU and the FPU control registers
Details how to configure the FPU's behavior and handle exceptions.
FPU pipeline and instruction timing
Explains the FPU pipeline structure and the timing of FP operations.
The MIPS32® DSP ASE
Features provided by the MIPS® DSP ASE
Highlights key features of the DSP ASE, including fractional types and saturating arithmetic.
The DSP ASE control register
Describes the DSPControl register for managing DSP operations and state.
DSP instructions
Details various DSP instructions, categorized by function and usage.
74K™ core features for debug and profiling
EJTAG on-chip debug unit
Covers the EJTAG unit for on-chip debugging, including communication and modes.
Watchpoints
Explains the CP0 watchpoint registers for monitoring memory accesses.
Performance counters
Details the hardware performance counters for system profiling and analysis.
PDtrace™ instruction trace facility
Describes the PDtrace system for tracing instruction execution and data flow.
References
74K™ core family manuals
Lists core-specific manuals and documentation for the 74K family.
CP0 register summary and reference
Register index by name
Table mapping CP0 register names to their numbers and page references.
Miscellaneous CP0 register descriptions
Provides descriptions for CP0 registers not covered in detail elsewhere.
Status register
Details the Status register, controlling CPU modes, interrupts, and extensions.
Exception control: Cause and EPC registers
Explains the Cause and EPC registers for exception handling.
Registers for CPU Configuration
Covers registers related to CPU configuration, including the Config register.
Registers for Cache Diagnostics
Describes registers used for testing and diagnosing cache behavior.
MIPS® Architecture quick-reference sheet(s)
General purpose register numbers and names
Lists general-purpose registers with their conventional names and usage.
User-level changes with Release 2 of the MIPS32® Architecture
Highlights new features and user-level access to hardware registers in MIPS32 Release 2.
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