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November 09, 2018
W65C816S
8/16–bit Microprocessor
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Table of Contents
Related Manuals for WDC W65C816S
Summarization of Contents
1 Introduction
1.1 Features of the W65C816S
Lists key features like low power, 24-bit address bus, and full 16-bit registers.
2 W65C816S Functional Description
2.3 Arithmetic and Logic Unit (ALU)
Performs all arithmetic and logic operations and address calculations.
2.8 Processor Status Register (P)
Contains status flags (C, N, V, Z) and mode select bits (M, X, D, I, E).
2.12 Pin Function Description
Details the function of each pin on the W65C816S package.
2.13 Abort (ABORTB)
Input to abort instructions, typically due to bus conditions.
2.18 Interrupt Request (IRQB)
Input signal to request an interrupt sequence after current instruction.
2.21 Non-Maskable Interrupt (NMIB)
Input initiating an interrupt sequence on a negative transition.
2.25 Reset (RESB)
Active low input to initialize the microprocessor and start program execution.
3 Addressing Modes
3.2 Stack
Stack memory range and its use in addressing modes.
3.3 Direct
Direct addressing modes used for registers and pointers, typically in Bank 0.
3.5 Data Address Space
Contiguous 16 MByte address space for data structures.
3.5.1 Absolute-a
Uses low order 16 bits from instruction, high order 8 bits from Data Bank Register.
3.5.18 Immediate-#
Operand is the second (and third) byte(s) of the instruction.
3.5.22 Stack-s
Refers to instructions pushing or pulling data from the stack.
4 Timing, AC and DC Characteristics
4.1 Absolute Maximum Ratings
Defines the absolute maximum voltage, current, and temperature limits for the device.
4.2 DC Characteristics TA = -40°C to +85°C
Specifies DC electrical characteristics over the operating temperature range.
6 Recommended W65C816S Assembler Syntax Standards
6.1 Directives
Assembler directives give directions to the assembler; this standard excludes their definitions.
6.3 The Source Line
Line structure for generating machine language instructions: label, opcode, operand, comment.
6.3.3 The Operand Field
Specifies how addresses, constants, and calculations are represented in the operand.
7 Caveats
7.1 Stack Addressing
Describes stack usage in Native and Emulation modes.
7.4 ABORTB Input
Specifies behavior and recommendations for the ABORTB input.
7.10 Switching Modes
Describes register changes when switching between Native and Emulation modes.
7.13 Wait for Interrupt (WAI) Instruction
WAI instruction pulls RDY low for low power mode; terminated by interrupts.
7.19 Interrupt Priorities
Defines the priority order for multiple simultaneous interrupts.
8 Hard Core Model
8.1 W65C816 Core Information
Provides core information, functional differences from W65C816S, and pin requirements.
9 Soft Core RTL Model
9.1 W65C816 Synthesizable RTL-Code in Verilog HDL
Describes the synthesizable RTL-Code model for ASIC design.
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