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EarthPeople Technology MAXPROLOGIC User Manual

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MaxProLogic Development System User Manual
MAXPROLOGIC DEVELOPMENT SYSTEM
The MaxProLogic is an FPGA development board that is designed to be user friendly and a great
introduction into digital design for Electrical Engineering students and hobbyists. This board
provides innovative methods of developing and debugging programmable logic code. It has been
designed from the ground up to provide the functionality needed for the demanding projects from
today's students and hobbyists. The board provides a convenient, user-friendly workflow by
connecting seamlessly with Altera's Quartus Prime Lite software. The user will develop the code
in the Quartus environment on a Windows Personal Computer. The programmable logic code is
loaded into the FPGA using only the Quartus Programmer tool.
The core of the MaxProLogic is the Altera MAX10 FPGA. This powerful chip has 4,000 Logic
Elements and 200 Kbits of Memory. The MAX10 is easily scalable from the entry level college
student to the most advanced projects like an audio sound meter with FFT. The MAX10 is in
Altera's line up of low cost, multi-function FPGA's.
Circuit designs, software and documentation are copyright © 2025, Earth People Technology,
Inc
Microsoft and Windows are both registered trademarks of Microsoft Corporation. Altera is a
trademark of the Altera Corporation. All other trademarks referenced herein are the property of
their respective owners and no trademark rights to the same are claimed.
http://www.earthpeopletechnology.com/
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  • Page 1 MAXPROLOGIC DEVELOPMENT SYSTEM User Manual The MaxProLogic is an FPGA development board that is designed to be user friendly and a great introduction into digital design for Electrical Engineering students and hobbyists. This board provides innovative methods of developing and debugging programmable logic code. It has been designed from the ground up to provide the functionality needed for the demanding projects from today’s students and hobbyists.

  • Page 2: Table Of Contents

    MaxProLogic Development System User Manual Contents Introduction ..........................4 User Setup ..........................5 MaxProLogic Description ....................... 5 Functional Block Diagram ....................6 MAXPROLOGIC SPECIFICATIONS ................6 FPGA ..........................7 Power Supply ........................8 Clock Domains......................10 Digital I/Os........................12 Analog Input ......................... 14 3.7.1...
  • Page 3 MaxProLogic Development System User Manual 3.10.5 Physical layer ......................34 3.10.6 Framing ......................... 34 3.10.7 Commands and Responses ..................34 3.10.8 Data ........................37 3.10.9 Handover ....................... 37 3.10.10 Initialisation ...................... 37 3.10.11 Reading ......................39 3.11 Power Input ........................40 3.12...

  • Page 4: Introduction

    Separately. 1 Introduction The MaxProLogic is an FPGA development board. It requires an external programmer to load user code into the flash of the FPGA. The core of the board is the MAX10 chip. It has a built in Flash for configuration and incorporates 8 channels of Analog to Digital Conversion. The board has two power options •...

  • Page 5: User Setup

    MaxProLogic Development System User Manual The MaxProLogic can be powered from a laptop with 2.5W of power. Or it can be run it from the +5V @ 2A wall USB chargers for 10W of power. The barrel connector can handle up to +5.5V @ 3 A for 16.5W of power.

  • Page 6: Functional Block Diagram

    MaxProLogic Development System User Manual 3.1 Functional Block Diagram MAXPROLOGIC SPECIFICATIONS • MAX 10 10M04SA FPGA From Altera 4,000 Logic Elements; • 2.2 Mbit On chip Flash; 189 Kbit On Chip SRAM 8 Analog Input • Channels; 12 bit; 1MSamples/Second 65 Available I/O’s at connectors •...

  • Page 7: Fpga

    Standard Programming Connector fits any Altera USB Blaster 3.3 FPGA The MaxProLogic includes the Altera 10M04SAE144C8G FPGA. It is an EQFP 144 pin package. This FPGA incorporates both the configuration flash and the ADC on the chip. This is different from conventional FPGAs as these two items are usually off chip. Access to the configuration flash is transparent to the user.

  • Page 8: Power Supply

    (EMIF) Inputs/Outputs 3.4 Power Supply The MaxProLogic is designed to be operated from one of the following power sources: • standard USB cable from Laptop/PC. • +5 VDC through USB-C cable. • +4.5 to +5.5 VDC supplied through the Barrel Connector.
  • Page 9 MaxProLogic Development System User Manual The TPS54229 is a very stable synchronous buck converter. This allows it to provide a fast transient response. You can view this response here: Page...

  • Page 10: Clock Domains

    On/Off controller is explained in section x. The default level for the PWR_ENABLE is high. The default level allows the power supply to turn on when power is applied to the board. 3.5 Clock Domains The MaxProLogic provides an external clock domain to the MAX10 FPGA, 50 MHz. The 50 Page...
  • Page 11 MaxProLogic Development System User Manual MHz oscillator is Part Number: ASDMB-50.000MHZ-LC-T and is a +3.3VDC device that provides a high speed clock to the FPGA. It is a CMOS device that provides a stable 50 MHz at ±50 ppm. This clock can be used directly in the user code or use it as an input to one of the PLL’s internal to the FPGA.

  • Page 12: Digital I/Os

    Supply Current 3.6 Digital I/Os The MaxProLogic has eight 10 pin headers that provide 64 digital Inputs and Outputs. All of the I/O’s are +3.3 VDC only. All I/O’s connect directly from the FPGA to one of the ten pin headers.
  • Page 13 MaxProLogic Development System User Manual All I/O’s are organized into separate banks of the FPGA. There are eight banks. These different banks provide different output speed technologies. Programmable Open Drain The optional open-drain output for each I/O pin is equivalent to an open collector output. If it is configured as an open drain, the logic value of the output is either high-Z or logic low.

  • Page 14: Analog Input

    MaxProLogic Development System User Manual 3.7 Analog Input The MaxProLogic features an analog input of eight buffered channels. Each channel has its own 1MHz Unity Gain Amplifier to provide isolation and filtering. The Unity Gain Amplifier provides the best isolation between channels when using a Sample and Hold ADC and a high speed multiplexor.
  • Page 15 MaxProLogic Development System User Manual Page...
  • Page 16 MaxProLogic Development System User Manual The Analog Inputs connect up to the MAX 10 FPGA using the following pins: Connector RefDes- MaxProLogic FPGA Signal Name MAX 10 Pin Number Pin Number Schematic Signal J11-1 J11-2 ANALOG_IN_1 USER_AIN[0] J11-3 ANALOG_IN_2 USER_AIN[1]...
  • Page 17 MaxProLogic Development System User Manual The ADC provide the MAX 10 devices with built-in capability for on-die temperature monitoring and external analog signal conversion. The ADC solution consists of hard IP blocks in the MAX 10 device periphery and soft logic through the Altera Modular ADC IP core. The ADC solution provides you with built-in capability to translate analog quantities to digital data for information processing, computing, data transmission, and control systems.
  • Page 18 MaxProLogic Development System User Manual In prescaler mode, the analog input can measure up to 3.0 V in dual supply Altera® MAX® 10 devices and up to 3.6 V in single supply Altera® MAX® 10 devices. The analog input scale has full scale code from 000h to FFFh. However, the measurement can only display up to full scale –...

  • Page 19: Voltage Representation Conversion

    MaxProLogic Development System User Manual 3.7.1 Voltage Representation Conversion Use the following equations to convert the voltage between analog value and digital representation. Conversion from Analog Value to Digital Code Digital Code=(VINVREF)×212 Digital Code=( )×2 Conversion from Digital Code to Analog Value )Analog Value=Digital Code×(VREF212)

  • Page 20: Adc Prescaler

    MaxProLogic Development System User Manual • Dedicated ADC analog input pin—pins with dedicated routing that ensures both dedicated analog input pins in a dual ADC device has the same trace length. • Dual function ADC analog input pin—pins that share the pad with GPIO pins.

  • Page 21: Adc Voltage Reference

    MaxProLogic Development System User Manual • Both ADC blocks share the same clock source for synchronization. • Both ADC blocks use different PLLs for redundancy. If each ADC block in your design uses its own PLL, the Altera Quartus Prime Fitter ®...

  • Page 22: Parameters Settings For Generating Altpll Ip Core

    MaxProLogic Development System User Manual 3.7.8 Parameters Settings for Generating ALTPLL IP Core Navigate through the ALTPLL IP core parameter editor and specify the settings required for your design. After you have specified all options as listed in the following table, you can generate the HDL files and the optional simulation files.
  • Page 23 MaxProLogic Development System User Manual 2. Connect the c0 signal from the ALTPLL IP core to the adc_pll_clock_clk port of the Altera Modular ADCIP core. 3. Connect the locked signal from the ALTPLL IP core to the adc_pll_locked_export port of the Altera Modular ADC IP core.

  • Page 24: I2C Sensor Connector

    3.8 I2C Sensor Connector The MaxProLogic includes an I2C Sensor connector. This connector is designed to accept inline six pin sensor boards that are popular with bread board connections. Page...
  • Page 25 MaxProLogic Development System User Manual The sensor is accessed through an I2C bus. This bus is connected to the FPGA through the following pins: Connector RefDes- MaxProLogic FPGA Signal Name MAX 10 Pin Number Pin Number Schematic Signal J14-1 +3.3V...
  • Page 26 These I2C signals can connect to any I2C device or Master. The user can implement code in the FPGA will perform either Master or Device functionality. The MaxProLogic Project DVD includes sample code to get the user started writing an I2C driver. This sample code is designed to connect to the TMP102 Temperature Sensor Breakout Board.

  • Page 27: User Leds

    MaxProLogic Development System User Manual 3.9 User LEDs The MaxProLogic includes eight user LEDs. The LEDs are directly driven from the FPGA. User code can implement any pattern on the LEDs by asserting a Ground to light up the diode and a...
  • Page 28 MaxProLogic Development System User Manual high to turn it off. The LEDs are located at the front of the board between the USB-C and Barrel connectors. Page...
  • Page 29 MaxProLogic Development System User Manual They use the +3.3V I/O’s along with a 220 Ohm series resistor for each LED. This provides the following current through the LEDS �� − �� �� �� �� ������ �� 3.3�� − 2.0�� ��...
  • Page 30 MaxProLogic Development System User Manual The User LEDs are available at the following pins: LED Number MaxProLogic FPGA Signal Name MAX 10 Pin Number Schematic Signal LED1 USER_LEDS[0] LED2 USER_LEDS[1] LED3 USER_LEDS[2] LED4 USER_LEDS[3] LED5 USER_LEDS[4] LED6 USER_LEDS[5] Page...

  • Page 31: Sd Card Interface

    The SD Connector uses a standard cell phone SD Card Connector. This connector has a mechanism that opens out away from the board on a hinge and allows the card to be inserted into the hinged door. Close the hinged door and pull it towards the front of the MaxProLogic to secure it.
  • Page 32 MaxProLogic Development System User Manual The SD Card signals are available at the following pins: SD Connector Pin MaxProLogic FPGA Signal Name MAX 10 Pin Number Number Schematic Signal P3-1 P3-2 P3-3 P3-4 P3-5 P3-6 P3-7 P3-8 Page...

  • Page 33: Sd Card Protocol

    MaxProLogic Development System User Manual 3.10.1 SD Card Protocol There's a ton of information out there on using the MMC/SD SPI protocol to access SD cards but not much on the native protocol. This page hopes to rectify that with information helpful to those implementing a SD host or trying to understand what they're seeing on an oscilloscope.

  • Page 34: Physical Layer

    MaxProLogic Development System User Manual 3.10.5 Physical layer All communication are at 3.3 V logic levels with 3.3 V being a high and 0 V being a low. CLK comes from the host and idles low. CMD and DAT are bidirectional and idle high. All are driven in a push/pull mode for speed.
  • Page 35 MaxProLogic Development System User Manual Stop bit The CRC is a 7 bit CRC with polynomial x + 1. A table driven form can be found in the Linux kernel under lib/crc7.c. Bitwise forms may be generated using with the...
  • Page 36 MaxProLogic Development System User Manual Start bit = 0 ▪ Transmitter = 1 ▪ Command = 55 (decimal) ▪ Argument = 00000000 ▪ CRC = 0x32 ▪ Stop bit = 1 ▪ The CRC can be generated by feeding 0x77, 0x00, 0x00, 0x00, 0x00 into the CRC function above.

  • Page 37: Data

    MaxProLogic Development System User Manual Note that this cards Relative Card Address (RCA) is 0xB368 3.10.8 Data Data has the following format: Value Name 4113 Start bit 4112-17 512*8 Data bits 16-1 Stop bit Note that this is for a typical transfer of a block of 512 bytes. The host knows from the command that was sent how many bytes to expect back.
  • Page 38 MaxProLogic Development System User Manual present then you will get a wired-OR response with 0x3F as the command and 0xFF as the CRC and stop bit. Note that this must be sent or SDHC cards will not respond to the...

  • Page 39: Reading

    MaxProLogic Development System User Manual 4000000000 CMD0 None 7700000000 CMD55 370000012083 Card ACMD41 6900100000 SEND_OP_COND 3F00FF8000FF busy 7700000000 CMD55 370000012083 Card 6900100000 is still ACMD41 3F00FF8000FF busy 7700000000 CMD55 370000012083 Card ACMD41 6900100000 SEND_OP_COND 3F80FF8000FF ready CMD2 4200000000 3F1D4144534420202010A0400BC1008 ALL_SEND_CID...

  • Page 40: Power Input

    FPGA. 3.12 On/Off Control The MaxProLogic is equipped with an On/Off circuit. This circuit consists of a push button switch that is momentary contact and a MAX16054 controller chip. The controller senses the change in state of the momentary switch and drives the output “PWR_ENABLE” signal to the +3.3 VDC power supply.
  • Page 41 MaxProLogic Development System User Manual Use the Pushbutton SW1 to turn the power on to the MaxProLogic. The TPS54229 Synchronous Buck Regulator will take any noisy input power and provide a smooth stable output. It has a fast transient response with a large inductor on the output.
  • Page 42 MaxProLogic Development System User Manual The MAX16054 Controller chip also has a ‘CLEAR’ input. This input allows secondary device to cause a shutdown. The CLEAR input has the following truth table: Clear Pin Output of TPS54229 High +3.3 V Page...

  • Page 43: Communications Interface

    MaxProLogic Development System User Manual The On/Off controller can be bypassed and allow the MaxProLogic to power up whenever power is applied. The JMP2 provides the bypass. Set the jumper to the ‘1’ position to use the On/Off pushbutton switch. Uses the ‘2’ position to allow the MaxProLogic to power up with board power.
  • Page 44 MaxProLogic Development System User Manual The MaxProLogic Communications Interface is compatible with both +5V and +3.3V Breakout Boards. The JMP1 provides a user selection jumper to select the +5V and +3.3V interface. There Page...
  • Page 45 MaxProLogic Development System User Manual are two 74LVC1G17 Schmitt Trigger chips to provide voltage level compatibility with the FPGA. The FPGA must run Verilog code to perform the full duplex UART communications. The code must decode in the incoming RX signal and produce the outgoing TX signals with an accuracy of greater than 99%.
  • Page 46 MaxProLogic Development System User Manual For the incoming RX signal, the FPGA must sample each bit of the protocol at four times per bit. This sampling rate is critical as the sending device clock and the receiving device clock are not synchronized.

  • Page 47: Jtag Interface

    3.14 JTAG Interface The MaxProLogic has a 5x2 header for use in programming the MAX10 FPGA via JTAG. The connector is located in the bottom right corner of the MaxProLogic. It is shrouded and keyed to allow easier insertion. Page...
  • Page 48 This connector uses the standard Altera Blaster connector pinout. The VCC(TRGT) is set to +3.3V on the MaxProLogic. There are no jumper settings to make in order to program the MAX10 FPGA. Just connect a compatible Blaster to the connector and the PC, then use the Quartus software to program the FPGA.

  • Page 49: Powering The Maxprologic

    4 Powering the MaxProLogic You can run the MaxProLogic from a laptop with 2.5W of power. Or you can run it from the +5V @ 2A wall USB chargers for 10W of power. The barrel connector can handle up to +5.5V @ 3 A for 15W of power.
  • Page 50 The current limit is around 4.7Amps. But, the MaxProLogic is only designed to handle 2Amps of current. So, damage may occur to the MaxProLogic if the user does not exercise care in design and use of the Inputs/Outputs.

  • Page 51: Installing Quartus

    MaxProLogic Development System User Manual Power the MaxProLogic directly from the wall charger. +5V@2A 5 Installing Quartus You must install Quartus Prime to configure the CycloFlex. Altera Quartus Prime must be downloaded from the Altera website. Download the Quartus Prime by following the directions in the Section Downloading Quartus.
  • Page 52 MaxProLogic Development System User Manual You will first need to apply for an account with Intel. Then use your login and password to access the download site. Click on the Download Windows Version. Scroll down the page to the “Downloads” section.
  • Page 53 MaxProLogic Development System User Manual Click on the “Download Quartus-lite-22.1 xxxxxx Windows Tar. Page...
  • Page 54 MaxProLogic Development System User Manual Click through the Legal Stuff. Page...
  • Page 55 MaxProLogic Development System User Manual This will start the download. Page...
  • Page 56 MaxProLogic Development System User Manual The file is 13.9 GB (or greater), so this could take a couple of hours depending on your internet connection. When download is complete, store the *.tar file in a directory on your PC. Page...
  • Page 57 MaxProLogic Development System User Manual Use a tool such as WinZip to Extract the *.tar file. Page...

  • Page 58: Quartus Installer

    MaxProLogic Development System User Manual The tool will unpack all files. 5.1.2 Quartus Installer When the unpacking finishes from the previous section, double click the setup.bat file in the download folder. Page...
  • Page 59 MaxProLogic Development System User Manual Click “Next” on the Introduction Window. Page...
  • Page 60 MaxProLogic Development System User Manual Click the checkbox to agree to the license terms. Then click “Next”. Page...
  • Page 61 MaxProLogic Development System User Manual Click “Next” and accept the defaults. At the Select Products Window, de-select the Quartus Prime Supbscription Edition by clicking on its check box so that the box is not checked. Then click on the check box by the Quartus Prime Web Edition (Free).
  • Page 62 MaxProLogic Development System User Manual Click “Next” to accept the defaults Page...
  • Page 63 MaxProLogic Development System User Manual Click “Next” to accept the defaults Page...
  • Page 64 MaxProLogic Development System User Manual Wait for the installation to complete. Page...
  • Page 65 MaxProLogic Development System User Manual Page...
  • Page 66 MaxProLogic Development System User Manual Click “Ok”, then click “Finish”. The Quartus Prime is now installed and ready to be used. Page...
  • Page 67 MaxProLogic Development System User Manual At this point the Quartus Prime Lite software is installed. Go to the Windows button and type in “quartus” at the search prompt. Page...
  • Page 68 MaxProLogic Development System User Manual The Windows Search should locate the installed version of Quartus. Click on the icon and the software should load properly. If this does not occur, contact Earth People Technology for support. There are three methods to contact EPT for support: https://www.earthpeopletechnology.com->Forums...

  • Page 69: Compiling, Synthesizing, And Programming The Fpga

    MaxProLogic Development System User Manual 6 Compiling, Synthesizing, and Programming the FPGA The FPGA on the EPT-10M04-AF-S2can be programmed with the Active Transfer Library and custom HDL code created by the user. Programming the FPGA requires the use of the Quartus Prime Lite software and a standard USB cable.
  • Page 70 MaxProLogic Development System User Manual Open Quartus Prime Lite by clicking on the icon Under Quartus, Select File->New Project Wizard. The Wizard will walk you through setting up files and directories for your project. Page...
  • Page 71 MaxProLogic Development System User Manual At the Top-Level Entity page, browse to the c:/altera/xxx/quartus/qdesigns directory to store your project. Type in a name for your project “EPT_10M04_AF_S2_Top”. Page...
  • Page 72 MaxProLogic Development System User Manual Select Next. At the Add Files window: Browse to the \Projects_HDL\EPT_10M04_AF_Blinky \src folder of the EPT USB-FPGA Development System CD. Copy the files from the \src directory. • EPT_10M04_AF_S2_Top.v Page...
  • Page 73 MaxProLogic Development System User Manual Select Next, at the Device Family group, select MAX II for Family. In the Available Devices group, browse down to 10M04SAE22 for Name. Page...
  • Page 74 MaxProLogic Development System User Manual Select Next, leave defaults for the EDA Tool Settings. Page...
  • Page 75 MaxProLogic Development System User Manual Select Next, then select Finish. You are done with the project level selections. Page...

  • Page 76: Selecting Pins And Synthesizing

    MaxProLogic Development System User Manual Next, we will select the pins and synthesize the project. 6.1.1 Selecting Pins and Synthesizing With the project created, we need to assign pins to the project. The signals defined in the top level file (in this case: EPT_10M04_AF_S2_Top.v) will connect directly to pins on the FPGA.
  • Page 77 MaxProLogic Development System User Manual At the Import Assignment dialog box, Browse to the \Projects_HDL\EPT_10M04_AF_Blinky \ EPT-10M04-AF-S2_Top folder of the EPT FPGA Development System DVD. Select the “EPT- 10M04-AF-S2_Top.qsf” file. Click Ok. Under Assignments, Select Pin Planner. Verify the pins have been imported correctly.
  • Page 78 MaxProLogic Development System User Manual Page...
  • Page 79 MaxProLogic Development System User Manual The pin locations should not need to be changed for EPT FPGA Development System. However, if you need to change any pin location, just click on the “location” column for the particular node you wish to change. Then, select the new pin location from the drop down box.
  • Page 80 MaxProLogic Development System User Manual http://www.altera.com/literature/hb/qts/qts_qii53018.pdf?GSA_pos=1&WT.oss_r=1&WT.oss=T imeQuest Timing Analyzer Browse to the \Projects_HDL\EPT_10M04_AF_Blinky \ EPT-10M04-AF-S2_Top folder of the EPT USB-FPGA Development System CD. Select the “EPT-10M04-AF-S2_Top.sdc” file. Copy the file and browse to c:\altera\xxx\quartus\qdesigns\EPT_10M04_AF_Blinky directory. Paste the file. Select the Start Compilation button.
  • Page 81 MaxProLogic Development System User Manual If you forget to include a file or some other error you should expect to see a screen similar to this: Page...
  • Page 82 MaxProLogic Development System User Manual Click Ok, the select the “Error” tab to see the error. Page...
  • Page 83 MaxProLogic Development System User Manual Review the source and/or database to remedy the error. Once the error has been fixed, re-run the Compile process. After successful completion, the screen should look like the following: Page...

  • Page 84: Programming The Maxprologic

    Configuring the FPGA is quick and easy. All that is required is a standard USB-C cable and a compatible Blaster Programmer. Connect the MaxProLogic to the PC, open up Quartus Prime Lite, open the programmer tool, and click the Start button. To program the MAX10 Configuration Flash, connect the Blaster and ensure the JTAG Driver is loaded for Quartus Prime Lite.
  • Page 85 MaxProLogic Development System User Manual If the project created in the previous sections is not open, open it. Click on the Programmer button. Page...
  • Page 86 MaxProLogic Development System User Manual The Programmer Window will open up with the programming file selected. Click on the Hardware Setup button in the upper left corner. The Hardware Setup Window will open. In the “Available hardware items”, double click on “EPT-Blaster v1.6b”.
  • Page 87 MaxProLogic Development System User Manual If you successfully double clicked, the “Currently selected hardware:” dropdown box will show the “EPT-Blaster v1.6b”. Page...
  • Page 88 MaxProLogic Development System User Manual Click on the “Add File” button Page...
  • Page 89 MaxProLogic Development System User Manual At the Browse window, double click on the output files folder. Page...
  • Page 90 MaxProLogic Development System User Manual Double click on the “EPT_10M04_AF_Top.pof” file. Click the Open button in the lower right corner. Page...
  • Page 91 MaxProLogic Development System User Manual Next, selet the checkbox under the “Program/Configure” of the Programmer Tool. Page...
  • Page 92 MaxProLogic Development System User Manual Click on the Start button to to start programming the FPGA. The Progress bar will indicate the progress of programming. Page...
  • Page 93 MaxProLogic Development System User Manual When the programming is complete, the Progress bar will indicate success. Page...
  • Page 94 MaxProLogic Development System User Manual At this point, the MAXPROLOGIC is programmed and ready for use. The eight LEDs on the front of the MAXPROLOGIC will blink one after the other. Page...

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