Page 1 User’s Manual µ µ µ µ PD77210 Family Digital Signal Processor Architecture µ µ µ µ PD77210 µ µ µ µ PD77213 Document No. U15807EJ2V0UM00 (2nd edition) Date Published May 2002 N CP(K) 2002 Printed in Japan...
Page 2 [MEMO] User’s Manual U15807EJ2V0UM...
Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5: Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION This manual is intended for users who understand the functions of µ PD77210 Family devices Target Readers and who design application systems (hardware and software) using these products. The µ PD77210 Family is the general name for the µ PD77210 and µ PD77213 devices. Unless functional differences are otherwise specified, the descriptions in this manual apply to all µ...
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right ××× (pin or signal name is overlined) Active low representation: Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplemental information Binary …...
Page 8: Table Of Contents
CONTENTS CHAPTER 1 GENERAL........................... 17 Comparison with µ µ µ µ PD77111 Family ......................17 1.1.1 High-speed operation ......................... 17 1.1.2 Low power consumption ........................17 1.1.3 Expanded peripheral functions ......................17 Features ................................. 18 1.2.1 DSP core kernel..........................18 1.2.2 Peripheral block..........................
Page 9 4.4.4 Interrupts .............................77 4.4.5 Error status register (ESR) ........................89 Data Addressing Unit.............................90 4.5.1 Block configuration ..........................90 4.5.2 Data memory space ..........................90 4.5.3 Instruction memory aliasing.........................94 4.5.4 External data memory map .........................95 4.5.5 Addressing mode ..........................97 Operation Unit ..............................108 4.6.1 Block configuration ..........................109 4.6.2 General-purpose registers and data formats..................109 4.6.3...
Page 10 5.8.1 PMT registers ........................... 189 5.8.2 PMT operation modes ........................191 5.8.3 PMT transfer steps ........................... 192 General-Purpose I/O Port (PIO) ........................193 5.9.1 General-purpose I/O port pins ......................193 5.9.2 General-purpose I/O port registers ....................194 5.9.3 Timing of general-purpose I/O port....................196 5.9.4 Example of port programming ......................
Page 11 Initial Reset Boot............................240 6.1.1 Boot mode specification ........................240 6.1.2 X memory boot ..........................241 6.1.3 Y memory boot ..........................242 6.1.4 XY memory boot..........................243 6.1.5 External data memory boot .......................244 6.1.6 Host boot ............................245 6.1.7 Serial boot ............................247 6.1.8 Non-boot............................247 Initial Reset Boot and PLL...........................248 Reboot ................................249 APPENDIX A INDEX..........................250 A.1 Terminology Index ............................250...
Page 12 LIST OF FIGURES (1/3) Figure No. Title Page 161-Pin Plastic Fine Pitch BGA ........................23 144-Pin Plastic LQFP............................. 25 Pin Configuration ............................27 From Power-On to User Program Execution ....................37 From Starting to Stopping the PLL......................... 40 Overall Block Configuration ........................... 42 DSP Core Kernel ............................
Page 13 LIST OF FIGURES (2/3) Figure No. Title Page 4-38 16-Bit Shift Accumulative Multiplication ......................120 4-39 Barrel Shifter Operations ..........................124 Peripheral Units ............................126 Block Diagram of TDM Serial Interface ......................130 Slots................................137 Expanded Slots.............................137 Timing of TDM Serial Interface ........................138 Block Diagram of Audio Serial Interface .......................140 Output Timing of Audio Serial Interface......................145 Input Timing of Audio Serial Interface......................146 ASO Operation When ASIO Operation Is Started (in Master Mode) ............147...
Page 14: List Of Figures
LIST OF FIGURES (3/3) Figure No. Title Page 5-42 Example of POWC Register Settings......................225 5-43 JTAG Pin Handling ............................227 5-44 Block Diagram of Expansion Interface......................228 5-45 Block Diagram of SD Card Interface ......................230 Boot from X Memory ............................ 241 Boot from Y Memory ............................
Page 15 LIST OF TABLES (1/2) Table No. Title Page Features of µ PD77210 Family Devices ......................20 Connection of Functional Pins ........................35 Connection of Non-Functional pin ........................36 Registers Connected to Main Bus ........................45 Functional Block and Bus ..........................45 Registers and Memories Connected to X Data Bus ..................46 Registers and Memories Connected to Y Data Bus ..................47 PLL Multiplication Rate Settings ........................49 PLL Lock Range Settings ..........................50...
Page 16 LIST OF TABLES (2/2) Table No. Title Page 5-20 PMT Transfer Channels and Target Peripherals ..................189 5-21 Bit Configuration of PMC ..........................190 5-22 Registers of General-Purpose I/O Port ......................193 5-23 Bit Configuration of PCD..........................194 5-24 Interrupt Controller’s Registers ........................201 5-25 Bit Configuration of ICR ..........................
Page 17: Chapter 1 General
CHAPTER 1 GENERAL The µ PD77210 Family, which is the successor to the µ PD77111 Family, is the general name used for the 16-bit fixed decimal digital signal processors (DSPs) µ PD77210 and µ PD77213. Features such as high speed and low power consumption make these devices suitable not only for voice processing in various mobile application sets but also for processing of signals from all types of media including music and video.
Page 18: Features
CHAPTER 1 GENERAL Features The µ PD77210 Family is compatible with the µ PD77111 Family’s operations and instruction set. The µ PD77210 Family also maintains binary level compatibility with the µ PD77111 Family’s software and middleware (except for parts that depend on the memory configuration and peripheral configuration). 1.2.1 DSP core kernel Functions...
Page 19 CHAPTER 1 GENERAL Note Memory space (space from paging function) • Instruction memory 32-bit width × 16-bit words × 64 pages • X data memory 16-bit width × 16-bit words × 64 pages • Y data memory 16-bit width × 16-bit words × 64 pages •...
Page 20 CHAPTER 1 GENERAL Table 1-1. Features of µ µ µ µ PD77210 Family Devices µ PD77210 µ PD77213 Instruction cycle 6.25 ns 8.33 ns Operating clock frequency (maximum) 160 MHz 120 MHz × 10 to 32 (×2 steps), × 40 to 64 (×8 steps) Clock circuit PLL multiplier circuit ÷...
Page 21: Ordering Information
CHAPTER 1 GENERAL 1.2.3 Ordering information Part Number Package µ PD77210F1-DA2 161-pin plastic fine pitch BGA (10 × 10) µ PD77210GJ-8EN 144-pin plastic LQFP (fine pitch) (20 × 20) µ PD77213F1-×××-DA2 161-pin plastic fine pitch BGA (10 × 10) µ PD77213GJ-×××-8EN 144-pin plastic LQFP (fine pitch) (20 ×...
Page 22: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS This chapter describes the pin connections and pin functions of the µ PD77210 Family. The pin names are shown below. ASCK: Audio serial clock input/output MWAIT: External data memory access wait ASI: Audio serial data input input ASIEN: Audio serial input enable...
Page 23: Pin Connection
CHAPTER 2 PIN FUNCTIONS Pin Connection The µ PD77213 pins are connected in the same way as the µ PD77210 except that some external memory pins are shared with the SD card interface. 161-pin plastic fine pitch BGA (10 × × × × 10) 2.1.1 •...
Page 24 CHAPTER 2 PIN FUNCTIONS Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name TSORQ P10/HD10/INT22 P5/INT11 P11/HD11/INT32 P2/INT20 P12/HD12/INT03 MA10 MA12 Note P1/INT10 MA15/Reserved Note MA19/SDCLK Note PLL0 MA18/SDCR STOPS TRST TICE ASIEN/MCLK MD12 MBSTB TSCK...
Page 25: 144-Pin Plastic Lqfp (Fine Pitch) (20 × 20)
CHAPTER 2 PIN FUNCTIONS 144-pin plastic LQFP (fine pitch) (20 × × × × 20) 2.1.2 • • • • µ PD77210GJ-8EN • • • • µ PD77213GJ-×××-8EN Figure 2-2. 144-Pin Plastic LQFP Note MA17/Reserved Note MA16/Reserved Note MA15/Reserved Note TRST MA14/SDDAT0 Note...
Page 26 CHAPTER 2 PIN FUNCTIONS Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name ASCK/BCLK Note P8/HD8/INT02 ASIEN/MCLK MA18/SDCR Note P9/HD9/INT12 MA19/SDCLK TRST P10/HD10/INT22 TSOEN MHOLDRQ I.C. P11/HD11/INT32 MHOLDAK I.C. P12/HD12/INT03 TSCK P13/HD13/INT13 TSIEN P14/HD14/INT23 MWAIT RESET...
Page 27: Pin Configuration
CHAPTER 2 PIN FUNCTIONS Pin Configuration Figure 2-3 shows the pin connections of the µ PD77210 family, classifying the pins by function. The pin configuration of the µ PD77213 is the same as the µ PD77210 except that an SD card interface has been added.
Page 28: Pin Functions
CHAPTER 2 PIN FUNCTIONS Pin Functions (1) Power supply pins Pin Name Pin No. Function Alternate- Function 144-Pin LQFP 161-Pin FBGA − − 18, 21, 23, 57, A7, A8, B7, H1, Power supply for DSP core (+1.5 V) 88, 123 J14, P7 These pins supply power to the DSP core.
Page 29 CHAPTER 2 PIN FUNCTIONS (3) Reset and interrupt pins Pin Name Pin No. Function Alternate- Function 144-Pin LQFP 161-Pin FBGA − RESET Input Internal system reset signal input This pin initializes the µ PD77210 Family. INT00 Input Maskable external interrupt input These pins input external interrupts.
Page 30 CHAPTER 2 PIN FUNCTIONS (4) External data memory interface Pin Name Pin No. Function Alternate- Function 144-Pin LQFP 161-Pin FBGA MA0 to 84, 85, M6, N6, N7, P8, Output Address bus of external data memory SDCLK, Note MA19 90 to 97, M7, M8, P9, N8, (3S) These pins output an address when the external data...
Page 31 CHAPTER 2 PIN FUNCTIONS (5) Timer Pin Name Pin No. Function Alternate- Function 144-Pin LQFP 161-Pin FBGA − TIMOUT Output Time out monitor This pin is asserted active when the timer times out. (6) Serial interface Pin Name Pin No. Function Alternate- Function...
Page 32: Host Interface
CHAPTER 2 PIN FUNCTIONS (7) Host interface Pin Name Pin No. Function Alternate- Function 144-Pin LQFP 161-Pin FBGA − Input Host address 1 This pin specifies a register that is accessed by the host interface pins (HD7 to HD0, or HD15 to HD0). •...
Page 33 CHAPTER 2 PIN FUNCTIONS (8) I/O port Pin Name Pin No. Function Alternate- Function 144-Pin LQFP 161-Pin FBGA General-purpose I/O port INT00 INT10 INT20 INT30 INT01 INT11 INT21 INT31 INT02/HD8 INT12/HD9 INT22/HD10 INT32/HD11 INT03/HD12 INT13/HD13 INT23/HD14 INT33/HD15 (9) Debugging interface Pin Name Pin No.
Page 34 CHAPTER 2 PIN FUNCTIONS (10) Others Pin Name Pin No. Function Alternate- Function 144-Pin LQFP 161-Pin FBGA − − I.C. 6, 7 B11, C10 Internally connected. Leave these pins open. − − − A1, A2, A13, No connection. A14, B1, B2, Leave these pins open.
Page 35: Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Connection of Unused Pins Connect the unused pins as shown in the table below. Table 2-1. Connection of Functional Pins Pin Name Recommended Connection STOPS, HALTS Output Leave open. CSTOP Input Connect to GND via a pull-down resistor. CLKOUT Output Leave open.
Page 36 CHAPTER 2 PIN FUNCTIONS Table 2-2. Connection of Non-Functional pin Pin Name Recommended Connection − I.C. Leave open. − Leave open. User’s Manual U15807EJ2V0UM...
Page 37: Chapter 3 Use Methods
CHAPTER 3 USE METHODS This chapter describes the flow of operations from power-on to actual execution of user program code in the µ PD77210 Family device, and also covers the general use of this device. For details, see the various function descriptions.
Page 38: Power-On
CHAPTER 3 USE METHODS 3.1.1 Power-on µ PD77210 Family devices have two power sources: the DSP core’s power supply (IV ) and the I/O power supply ). IV is a 1.5-V power supply while EV is a 3-V power supply. We recommend that both should be started at the same time.
Page 39: Standby Mode
CHAPTER 3 USE METHODS Standby Mode When the DSP program is idle, two standby modes are available as a means of reducing current consumption. An instruction is executed to switch to a standby mode. Execute a HALT instruction to switch to HALT mode. This will automatically switch the clock source to the divider. If the clock source has already been switched to the divider, there is no change in the operating clock.
Page 40 CHAPTER 3 USE METHODS Figure 3-2. From Starting to Stopping the PLL Start PLL µ Wait for lockup (300 Select PLL Deselect divider These steps may be performed automatically during start and boot operations. Set division rate Select divider Normal operation Deselect PLL Stop PLL (if necessary) HALT/STOP...
Page 41: Chapter 4 Architecture
CHAPTER 4 ARCHITECTURE This chapter describes the architecture of µ PD77210 Family devices. Overall Block Configuration This section divides the physical structure of the µ PD77210 Family into several functional blocks for explanation. The µ PD77210 Family consists of the following internal units: •...
Page 42: Dsp Core Kernel
CHAPTER 4 ARCHITECTURE Figure 4-1. Overall Block Configuration Peripheral units X data bus External External memory memory I/O Y data bus SD card Note Serial I/O X data memory Y data memory (audio) (RAM, ROM) (RAM, ROM) DSP core kernel Serial I/O (TDM) Instruction bus...
Page 43 CHAPTER 4 ARCHITECTURE Figure 4-2. DSP Core Kernel X data bus Y data bus X data memory Y data memory R0 to R7 X data memory Y data memory data addressing data addressing unit unit ALU (40) BSFT 16 × 16 + 40 → 40 Data memory units Main bus Operation unit...
Page 44: Buses
CHAPTER 4 ARCHITECTURE Buses A bus transfers data between external devices and the processor. The µ PD77210 Family is provided with the following four types of buses: • Main bus • X data bus • Y data bus • Peripheral ↔ memory transfer bus 4.2.1 Main bus (1) Function...
Page 45: Data Bus
CHAPTER 4 ARCHITECTURE (2) Registers connected to main bus The table shown below lists the registers connected to the main bus. Table 4-1. Registers Connected to Main Bus Register Name Assembler-Reserved Name Load (L)/Store (S) General-purpose register R0L to R7L (L part of R0 to R7) Data pointer DP0 to DP7 Index register...
Page 46 CHAPTER 4 ARCHITECTURE (2) X data bus This 16-bit bus connects the general-purpose registers, X data memory, and the bus from the internal peripherals. This bus transfers data when the following instructions are executed: • Parallel load/store instruction (for X data memory) •...
Page 47: Peripheral ↔ Memory Transfer Bus
CHAPTER 4 ARCHITECTURE (3) Y data bus This 16-bit bus connects the general-purpose registers, Y data memory, and the bus from the internal peripherals. This bus transfers data when the following instructions are executed: • Parallel load/store instruction (for Y data memory) •...
Page 48: System Control Units
CHAPTER 4 ARCHITECTURE System Control Units The following basic functions, which support the digital signal processor operations of the µ PD77210 Family, are called system control units: • Clock generator • Reset function • Pipeline architecture • Standby function User’s Manual U15807EJ2V0UM...
Page 49: Clock Generator
CHAPTER 4 ARCHITECTURE 4.3.1 Clock generator The clock generator is a circuit that generates and controls the system clock that is supplied to the CPU. It consists of a PLL, divider, and clock controller. The internal system clock is generated from an external clock that is input via the CLKIN pin. This system clock provides the reference timing within the device.
Page 50: Reset Function
CHAPTER 4 ARCHITECTURE The clock that is input to the PLL controller is multiplied from 10 to 64 times. Make sure that the multiplied clock frequency is specified within the PLL lock frequency range stipulated in the specifications. The PLL lock frequency ranges from 80 MHz to 160 MHz.
Page 51: Reset Operation Timing
CHAPTER 4 ARCHITECTURE Figure 4-3. Reset Operation Timing (1/2) CLKIN RESET Boot program User program Note 2 HALTS Depends on user program Depends on user program STOPS CSTOP CLKOUT Depends on user program Depends on user program TIMOUT Note 3 PLL0 to PLL3 P0 to P3/ Note 3...
Page 52 CHAPTER 4 ARCHITECTURE Figure 4-3. Reset Operation Timing (2/2) CLKIN RESET Boot program User program Note 2 Depends on user program TSORQ TSOEN TSIEN TSIAK Depends on boot mode/user program HA0 to HA1 Depends on user program Depends on boot mode/user program Note 3 HD0 to HD7 Depends on boot mode/user program...
Page 53 CHAPTER 4 ARCHITECTURE Table 4-8. Peripheral Registers to Be Initialized and Their Initial Values Register Name Initial Value SST1 0x00C2 TSST 0x0005 TFMT 0x0000 TTXL, TTXH, TRXL, TRXH 0xFFFF SST2 0x0002 ASST 0x8012 0x0301 MSHW 0x0000 MCST 0x0000 MWAIT 0xFFFF PMC0 to PMC7 0x0000 PCD0 to PCD3...
Page 54: Pipeline Architecture
CHAPTER 4 ARCHITECTURE 4.3.3 Pipeline architecture The µ PD77210 Family employs pipeline architecture to enhance the execution speed. Generally, one instruction completes its processing via several machine cycles each of which performs elemental processing. The instructions of the µ PD77210 Family have the following three machine cycles: F: Instruction fetch cycle Reads an op code from the instruction memory.
Page 55 CHAPTER 4 ARCHITECTURE Figure 4-4. Pipeline Image (a) Pipeline image 1 1 instruction cycle cycle cycle cycle Time Instruction J Instruction I Instruction H Instruction K Instruction J Instruction I Instruction L Instruction K Instruction J (b) Pipeline image 2 Time n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 Instruction 1...
Page 56 CHAPTER 4 ARCHITECTURE (1) Successive MAC, ALU, Barrelshifter operations When an instruction performing arithmetic/logic operations uses the result of the operation executed by the preceding instruction as an input operand, the result of the operation is written to a general-purpose register and, at the same time, input to the operation unit for the operation by the subsequent instruction.
Page 57: Standby Functions
CHAPTER 4 ARCHITECTURE 4.3.4 Standby functions µ PD77210 Family devices include standby functions that stop operation of the devices to reduce current consumption. Instructions are used to set a standby status, and a device whose status is “standby” is said to be in standby mode.
Page 58 CHAPTER 4 ARCHITECTURE (2) Standby mode set by STOP instruction STOP mode is set by executing a STOP instruction. When this occurs, the device’s current consumption is reduced by several hundred µ A (when PLL has been stopped). The steps for setting STOP mode and recovering from STOP mode are as follows.
Page 59: Program Control Unit
CHAPTER 4 ARCHITECTURE Program Control Unit This unit controls program execution. Data can be loaded from or stored to the registers in this unit via the main bus. This unit plays a role in execution of the following instructions: • General instruction execution •...
Page 60: Program Execution Control Block
CHAPTER 4 ARCHITECTURE 4.4.2 Program execution control block Program execution is controlled by the following registers: • Program counter (PC) • Stack (STK) • Stack pointer (SP) (1) Program counter (PC) This is a 16-bit register that holds the address of the instruction currently under execution when the program is executed.
Page 61: Instruction Memory Map
CHAPTER 4 ARCHITECTURE (b) Instruction memory An instruction memory map of µ PD77210 Family devices is shown below. There is a method whereby instruction areas can be accessed as data areas. For details, see 4.5.3 Instruction memory alias. Figure 4-6. Instruction Memory Map µ...
Page 62 CHAPTER 4 ARCHITECTURE (2) Stack (STK) and stack pointer (SP) Stack (STK) is a register file dedicated to saving/restoring program counter (PC) and consists of 16 bits by 15 levels. It is used to: • Save return address when a subroutine is called •...
Page 63 CHAPTER 4 ARCHITECTURE Figure 4-7. Normal Operation of PC Time n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 Instruction 1 (address n) Instruction 2...
Page 64 CHAPTER 4 ARCHITECTURE <2> Branch viewed from PC setting format The branch instructions can be classified into the following two types when viewed from the format in which the branch destination address is set to the PC: • Immediate jump/call This format is called immediate jump or immediate call.
Page 65 CHAPTER 4 ARCHITECTURE Table 4-12. Classification of Branch Instructions Instruction Name Condition Judgment Address Specification Word Length Instruction Cycles Jump instruction Unconditional PC relative Conditional Unconditional Register indirect absolute Conditional Subroutine call instruction Unconditional PC relative Conditional Indirect subroutine call instruction Unconditional Register indirect absolute Conditional...
Page 66 CHAPTER 4 ARCHITECTURE Figure 4-8. Timing of Unconditional Immediate Jump Clock addr instruction Next — instruction Instruction at JMP jif3 destination Next jif4 instruction Figure 4-9. Timing of Unconditional Indirect Jump Clock instruction addr Next — instruction Next — instruction Instruction jif4 at JMP...
Page 67 CHAPTER 4 ARCHITECTURE Figure 4-10. Timing of Conditional Immediate Jump (Condition Satisfied: Branch) Clock Conditional addr idec instruction Next — instruction Next — instruction Instruction jif4 at JMP destination Next jif5 instruction Figure 4-11. Timing of Conditional Immediate Jump (Condition Not Satisfied: Pass) Clock Conditional idec...
Page 68 CHAPTER 4 ARCHITECTURE (c) Operation of subroutine call/return Subroutine call is executed by the CALL instruction. When the CALL instruction is executed, execution branches in the following procedure: <1> The value of SP is incremented (pre-increment). <2> The value of PC (address next to the CALL instruction) is saved to the STK indicated by SP. <3>...
Page 69: Flow Control Block
CHAPTER 4 ARCHITECTURE 4.4.3 Flow control block In general, a high-level language provides sophisticated flow control syntax (e.g., for loop and while loop of the C language). The µ PD77210 Family is provided with hardware that allows this flow control to be directly described as assembly instructions, and performs loop/repeat operation without any timing overhead.
Page 70 CHAPTER 4 ARCHITECTURE • Loop stack pointer (LSP) This pointer indicates the current position of LSTK. Although this is a 16-bit register, the value that can be set to it is 0 to 4. The LSP value can be input/output to/from the main bus with inter-register transfer instruction. The LSP value becomes 0 by reset.
Page 71 CHAPTER 4 ARCHITECTURE (1) Repeat function The repeat function that is written by the REP instruction realizes repetition of one instruction on a count basis. The instruction to be repeated the repeat target instruction, follows immediately the REP instruction itself. (a) Format of repeat counter (RC) Figure 4-12 shows the format of the repeat counter (RC).
Page 72: Repeat Execution Timing (Repetition Of 2 Times)
CHAPTER 4 ARCHITECTURE (c) Procedure of repeat function execution When the REP instruction is executed, the repeat function is implemented in the following procedure. <1> The number of repetitions given as the parameter of the REP instruction is set to RC. <2>...
Page 73 CHAPTER 4 ARCHITECTURE (2) Loop function The loop function that is described by using the LOOP instruction realizes loop flow of an instruction group consisting of 2 to 255 instructions on a count basis. Nesting of loop is supported by a four level hardware loop stack.
Page 74 CHAPTER 4 ARCHITECTURE (c) Loop function execution procedure When the LOOP instruction is executed, the loop function is implemented in the following procedure: <1> When loop is started 1. The value of LSP is incremented (pre-increment). 2. The current LSA, LEA, and LC are saved to LSTK indicated by LSP. 3.
Page 75: Loop Execution Timing (Example Of 2 Loops Operation)
CHAPTER 4 ARCHITECTURE (d) Timing of loop execution (example of two loops operation) Figure 4-16 shows an example of the LOOP instruction execution timing. In this example, two loops operation in which a group of two instructions is executed only once is performed. Figure 4-16.
Page 76 CHAPTER 4 ARCHITECTURE (e) Software loop stack Performing a loop of five or more levels will cause the occurrence of a loop stack overflow. consequent loss of the return address means that a normal loop operation can no longer be performed. When it is apparent that loop processing with five or more levels is about to occur, saving the contents of the loop stack (LSTK) to the memory before it overflows will enable normal operation, even if a further loop is performed.
Page 77: Interrupts
CHAPTER 4 ARCHITECTURE 4.4.4 Interrupts µ PD77210 Family devices feature powerful interrupt functions. They fall into two types: interrupt functions for the DSP core kernel and interrupt controller functions for peripherals. The following describes the interrupt functions for the DSP core kernel. For description of the interrupt controller functions for peripherals, see 5.10 Interrupt Controller (INTC).
Page 78 CHAPTER 4 ARCHITECTURE (4) Interrupt vectors All interrupt factors have a fixed entry point (called a vector). The vector for each interrupt factor is set sequentially from the start address position (address 0x200) in the internal instruction area, which configures a 64-word table.
Page 79 CHAPTER 4 ARCHITECTURE (b) Example of interrupt vector processing An example of interrupt vector processing is shown below. ; Definitions #define SI1 0x3800 ; Address of serial input register #define SO1 0x3800 ; Address of serial output register #define ICR4 0x3884 ;...
Page 80 CHAPTER 4 ARCHITECTURE (5) Interrupt control software Interrupts are controlled by the following registers (refer to Figure 4-5 Program Control Unit): • Status register (SR) • Interrupt enable flag stack register (EIR) (a) Status register (SR) This is a 16-bit register that enables or disables all the interrupts (general interrupt enable/disable), and enables or disables each interrupt cause separately.
Page 81 CHAPTER 4 ARCHITECTURE The following shows on example of changing interrupt enable flag (enabled →disabled). Initial status: EI = 0 ; (interrupt enabled) R0L = EIR R0 = R0 | 0x8000 EIR = R0L Next instruction May branch to interrupt servicing Instruction that follows Caution To rewrite the EP and EB flag, be sure to disable all the interrupts (EI = 1).
Page 82 CHAPTER 4 ARCHITECTURE (b) Interrupt enable flag stack register (EIR) This 16-bit register stacks the general interrupt enable flags. When a bit of this register is 0, the corresponding interrupt is enabled; when the bit is 1, the interrupt is disabled. The values of EIR can be read and written by executing the register-to-register transfer instruction.
Page 83 CHAPTER 4 ARCHITECTURE (c) EIR and multiple interrupts As described earlier, a multiple interrupt system can be configured by using the EIR register. This paragraph describes the concept of multiple interrupts, taking an example shown in Figure 4-17 and focusing on EIR. Figure 4-17.
Page 84 CHAPTER 4 ARCHITECTURE (d) Differences between SR and EIR The most significant three bits of the SR and EIR registers (EI, EP, and EB) are accessed as common bits. The EI bit directly enables or disables the current interrupt, and therefore care must be exercised in manipulating this bit.
Page 85: Interrupt Acknowledging Timing
CHAPTER 4 ARCHITECTURE (6) Interrupt sequence (a) Acknowledging an interrupt When an interrupt has been acknowledged, the following operations are performed: • An instruction that was fetched immediately before the interrupt has been acknowledged is kept pending. • The EIR register is shifted 1 bit to the right to stack 1 level. •...
Page 86 CHAPTER 4 ARCHITECTURE (b) Returning from interrupt When the RETI instruction (interrupt return) is executed, the following are processed in two to three instruction cycles, and execution returns from the interrupt servicing routine. • The value of STK indicated by SP is restored to PC. •...
Page 87 CHAPTER 4 ARCHITECTURE (7) Delaying interrupt acknowledgment In the course of acknowledging an interrupt, registers SP, STK, and PC are automatically managed. To prevent conflicts with instructions that address these registers, acknowledging an interrupt is delayed when any of the following instructions that may cause such a conflict is executed.
Page 88 CHAPTER 4 ARCHITECTURE (b) Instructions generating delay of two instruction cycles The following instructions cause a delay of interrupt acknowledgment of two instruction cycles: • Decoding of conditional JMP instruction (PC-relative jump by immediate data) • Decoding of conditional CALL instruction (PC-relative jump by immediate data) •...
Page 89: Error Status Register (Esr)
CHAPTER 4 ARCHITECTURE (8) Conflict and recording of interrupt (a) Recording interrupt When an interrupt has been acknowledged, an interrupt servicing program is executed. During the execution, the global interrupt enable flag “EI” is automatically set to 1 (disable). Therefore, if another interrupt occurs during this period, it is not acknowledged immediately, but is recorded classified by the cause.
Page 90: Data Addressing Unit
CHAPTER 4 ARCHITECTURE Data Addressing Unit Generally, a DSP is required to access a large quantity of data flexibly and efficiently. The µ PD77210 Family is provided with dedicated data addressing units to efficiently access the data memory spaces. 4.5.1 Block configuration Figure 4-22 is the block diagram of the data address unit.
Page 91: Data Memory Map
CHAPTER 4 ARCHITECTURE (1) X and Y memory spaces The devices of the µ PD77210 Family have two independent data memory spaces: X and Y. These spaces are respectively accessed via the X and Y data buses (refer to 4.2.2 Data bus). The features of these memory spaces are as follows: •...
Page 92 CHAPTER 4 ARCHITECTURE (2) Internal data memory As is shown in Figure 4-23, the 32-Kword area that starts from address 0 (in the µ PD77210) or the 18-Kword area that starts from address 0 (in the µ PD77213) functions as an internal area that has been mapped within the device (the peripheral area is from address 0x3800 to address 0x3FFF).
Page 93 CHAPTER 4 ARCHITECTURE (4) Restrictions on simultaneous access µ PD77210 Family devices are able to access two objects in the X and Y memory spaces at the same time, such as through parallel loading, but such simultaneous access is subject to the following restrictions. •...
Page 94: Instruction Memory Aliasing
CHAPTER 4 ARCHITECTURE 4.5.3 Instruction memory aliasing Pages with aliases in instruction memory exist in the data page memory, and when those pages are specified in the data page register instruction memory contents can be accessed as data. Figure 4-24 shows an image of such an alias. Since the instruction memory has 32-bit width while the data memory has 16-bit width, the lower 16 bits of the instruction memory contents are aliased in X memory and the higher 16 bits of the instruction memory contents are aliased in Y memory.
Page 95: External Data Memory Map
CHAPTER 4 ARCHITECTURE 4.5.4 External data memory map An external data memory space of 1 Mword × 16 bits is supported. The two access methods are as follows. (1) Access using page memory (when DPR = 0x3F) as a window (2) Access via the MIO data register (MDT) For description of the second method, see 5.7 External Data Memory Interface (MIO).
Page 96 CHAPTER 4 ARCHITECTURE Figure 4-25. Image of Access to External Data Memory Map External data memory 0xFFFFF Internal data memory 0xFFFF External data memory Access area paging area (32 Kwords) DPR = 0x3F 0x8000 0x7FFF Data RAM area (16 Kwords) 0x4000 0x3FFF Peripheral...
Page 97: Addressing Mode
CHAPTER 4 ARCHITECTURE 4.5.5 Addressing mode The µ PD77210 Family is provided with a powerful architecture to realize high-speed, flexible data memory access. The X and Y memory areas are addressed by completely independent but functionally identically addressing units. This subsection describes the architecture and addressing modes implemented. (1) Function of each part of addressing unit The functions of the blocks (see Figure 4-22 Data Addressing Unit) and the registers in the addressing unit are as follows.
Page 98 CHAPTER 4 ARCHITECTURE (2) Types of addressing modes The data memory addressing modes are hierarchically classified below. There are one type of direct addressing mode and seven types of indirect addressing modes that are implemented by using data pointers (DPs) as the base address indicator. •...
Page 99 CHAPTER 4 ARCHITECTURE (b) Indirect addressing In all the indirect addressing modes, the DPn register (data pointer) is used. The basic features of indirect addressing are summarized below. • As the address value, the current value of specified DPn is output in all the modes except the bit reverse index addition mode.
Page 100 CHAPTER 4 ARCHITECTURE <3> *DPn− − − − − − − − (post decrement) The memory is accessed with the value of DPn. The value of DPn is decremented (Ð1) after the access has been completed. Example: R3E = *DP1--; 8-bit data (the lower 8 bits of the 16 bits) is loaded from the X memory address indicated by the value of DP1 to the E part (higher 8 bits) of R3, and then the value of DP1 is decremented.
Page 101 CHAPTER 4 ARCHITECTURE <6> *!DPn## (pre-bit reverse and post index addition) The memory is accessed by using the value that reverses the order of the DPn values, as shown in Figure 4-26, and the value of DNn is added to DPn after the access has been completed. Note that the value of DNn having the same number as that of DPn must be added to DPn (for example, DN1 to DP1).
Page 102 CHAPTER 4 ARCHITECTURE <8> Modifying data pointers Table 4-17 summarizes how the data pointers are modified as a result of accessing the memory in the above addressing modes. Table 4-17. Modifying Data Pointers (a) Operation Example Operation No modification DPn ← DPn + 1 DPn++ DPn−...
Page 103 CHAPTER 4 ARCHITECTURE <9> Modulo index addition and cyclic buffer The modulo index addition mode is provided for configuring a cyclic buffer (also called a ring buffer). • • • • Rule of operation After the memory has been accessed by using the value of DPn, DPn is modified. At this time, the operation is performed according to the following rules: (1) Executes operation of DP = DP...
Page 104 CHAPTER 4 ARCHITECTURE • • • • Meaning The ordinary modulo operation can be considered as the mapping shown in Figure 4-28. Figure 4-28. Mapping of Ordinary Modulo Operation − − M + 2 M + 1 − − − −...
Page 105 CHAPTER 4 ARCHITECTURE The difference between the two in terms of the range is that the usable buffer size in Figure 4-28 is M, while it is M + 1 in Figure 4-29, where the value set to DMa is M, because the range in this case corresponding to the size of the buffer.
Page 106 CHAPTER 4 ARCHITECTURE • • • • Example of modulo index addition An example of operation process when a cyclic buffer is configured by using modulo index addition is shown below. Example 1. DMX=0x7; DN0=1; DP0=0x0; At this time, the value of DP0 is updated as follows by means of modulo index addition: DP0=0x0 ↓...
Page 107 CHAPTER 4 ARCHITECTURE Example 2. DMX=0xA; DN0=3; DP0=0x10; At this time, the value of DP0 is updated as follows by means of modulo index addition: DP0=0x10 ↓ 0x10+3 DP0=0x13 ↓ 0x13+3 DP0=0x16 ↓ 0x16+3 DP0=0x19 ↓ 0x19+3=0x1C → 0x1C−(0xA+1)=0x11 DP0=0x11 ↓...
Page 108: Operation Unit
CHAPTER 4 ARCHITECTURE Operation Unit The general-purpose registers in this unit are source of all operands and destination of all results of arithmetic/logic operations. The general-purpose registers are connected to the • Main bus for inter-register transfers • X and Y data bus for data exchange with the data memories and peripheral registers All kinds of arithmetic/logic operations which are part of the following instruction types are carried out in the operation unit: •...
Page 109: Block Configuration
CHAPTER 4 ARCHITECTURE 4.6.1 Block configuration Figure 4-30 is the block diagram of the operation unit. Figure 4-30. Operation Unit X data bus (16 bits) Y data bus (16 bits) Immediate value 0/1/16 bits MSFT R0 to R7 (40 bits × 8) BSFT Main bus (16 bits) R0 to R7: General-purpose registers...
Page 110 CHAPTER 4 ARCHITECTURE (1) Partitioning of the general-purpose registers Although a general-purpose register consists of 40 bits, the register is divided into three parts, as follows, so that only a specified part of the register can be used to transfer and load/store data or to execute arithmetic operations.
Page 111 CHAPTER 4 ARCHITECTURE Figure 4-32 shows data exchange between general-purpose registers and data memory. Figure 4-32. Data Exchange Between General-Purpose Registers and Data Memory Number format in Operation General-purpose register Memory general register examples Memory General-purpose register x/y memory 16 bits unsigned Unsigned multiply 3231...
Page 112 CHAPTER 4 ARCHITECTURE (2) Numeric format The general-purpose registers of the µ PD77210 Family can process fixed-point and integer data. architecture places an emphasis on operations of fixed-point data, however. (a) Fixed-point format The fixed-point format uses the position between bits 31 and 30 as the decimal point. Fixed-point data can be expressed in three ways: in 40-bit, 32-bit, and 16-bit units.
Page 113: Operation Functions Of Multiply Accumulator (Mac) And Mac Input Shifter (Msft)
CHAPTER 4 ARCHITECTURE 4.6.3 Operation functions of multiply accumulator (MAC) and MAC input shifter (MSFT) The multiply accumulator performs the following functions: • Multiplication MPY: ro = rh * rh’ • Extends multiplication and its result to 40 bits and adds the result to specified general-purpose register MADD: ro = ro + rh * rh’...
Page 114 CHAPTER 4 ARCHITECTURE (a) Signed-signed multiply Both of the two operands are of signed 16-bit fixed-point type. Therefore, data is set to the H part of a general-purpose register whose bit 31 indicates the sign. A representation of this operation process is illustrated in Figure 4-33.
Page 115 CHAPTER 4 ARCHITECTURE (b) Signed-unsigned multiply One of the two operands is set to the H part of a general-purpose register in the 16-bit fixed-point type, where bit 31 of the register indicates a sign. The other parameter is set to the L part of a general-purpose register in the integer format.
Page 116 CHAPTER 4 ARCHITECTURE (c) Unsigned-unsigned multiply Both of the two operands are set to the L parts of general-purpose registers in the integer format. Figure 4-35 shows the image of this operation process. Caution There is no exclusive instruction that executes this operation. This operation is performed as part of the unsign-unsign multiply add instruction.
Page 117: Accumulative Multiplication
CHAPTER 4 ARCHITECTURE (2) Accumulative multiplication function (trinomial operation) All the trinomial operations executed by the µ PD77210 Family are accumulative multiplication. accumulative multiplication can be implemented in the following three ways, depending on the shift command to the register that is used for the accumulative operation (two accumulative operations, accumulative addition and accumulative subtraction, can be executed, however).
Page 118 CHAPTER 4 ARCHITECTURE (a) Accumulative multiplication The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to respectively subtracted from a 40-bit fixed-point operand. The related instructions are: MADD: ro = ro + rh * rh’ MSUB: ro = ro −...
Page 119 CHAPTER 4 ARCHITECTURE (b) 1-bit shift accumulative multiplication The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to a 1 bit right shifted 40-bit fixed-point operand. The related instruction is: MAS1: ro = (ro>>1) + rh * rh’ Figure 4-37 shows the image of this operation: Figure 4-37.
Page 120 CHAPTER 4 ARCHITECTURE (c) 16-bit shift accumulative multiplication The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to a 16 bit right shifted 40-bit fixed-point operand. The related instruction is: MAS16: ro = (ro>>16) + rh * rh’ Figure 4-38 shows the image of this operation: Figure 4-38.
Page 121: Operation Functions Of Arithmetic And Logic Unit (Alu)
CHAPTER 4 ARCHITECTURE 4.6.4 Operation functions of arithmetic and logic unit (ALU) The arithmetic and logic unit (ALU) executes an arithmetic or logical operation on two or one 40-bit input data, and outputs one 40-bit data. As both two operands for a binomial operation, general-purpose registers can be specified, or a register can be specified as one of the operands with immediate data specified as the other (immediate data cannot be used with the LT instruction, however).
Page 122 CHAPTER 4 ARCHITECTURE (2) Logical operation (a) Binomial logical operation The following binomial logical operation instructions are available. For each instruction, refer to µ µ µ µ PD77016 Family Instructions User’s Manual. • And instruction (AND) • Immediate and instruction (IAND) •...
Page 123: Operation Functions Of Barrel Shifter (Bsft)
CHAPTER 4 ARCHITECTURE 4.6.5 Operation functions of barrel shifter (BSFT) The barrel shifter (BSFT) executes shift operations. All the shift operations are binomial operations. The BSFT outputs any shift pattern as 40-bit data in one instruction cycle in response to 40-bit input data. As both two operands for a binomial operation, general-purpose registers can be specified, or a register can be specified as one of the operands with immediate data specified as the other.
Page 124 CHAPTER 4 ARCHITECTURE (2) Shift operation function Figure 4-39 shows each BSFT operations. Figure 4-39. Barrel Shifter Operations Shift number: n = 0 to 39, specified by - immediate value - bit 0 to 5 of rl part of general-purpose register •...
Page 125: Chapter 5 Peripherals
CHAPTER 5 PERIPHERALS The following peripheral interface functions are included in all µ PD77210 Family products. These peripheral units can be handled via registers that have been mapped to internal data areas in µ PD77210 Family devices. • Time division multiplexing (TDM) serial interface: TSIO •...
Page 126: Block Configuration
CHAPTER 5 PERIPHERALS Block Configuration Figure 5-1 shows the block configuration of the peripheral units. Figure 5-1. Peripheral Units Expansion I/O To X and Y data buses External MD0 to MD15 memory I/O Serial I/O ASO, ASI (audio) Serial I/O TSO,TS1 (TDM) To X and Y data memory...
Page 127: Peripheral Registers
CHAPTER 5 PERIPHERALS Peripheral Registers The peripheral registers and their mapping in the memory space are listed in Table 5-1. Table 5-1. Memory Mapping of Peripheral Registers (1/3) X/Y Memory Address Register Name Function Peripheral Name 0x3800 TSDT/SDT1 TDM serial data register/serial data register 1 TSIO (SIO1) 0x3801 SST1...
Page 128 CHAPTER 5 PERIPHERALS Table 5-1. Memory Mapping of Peripheral Registers (2/3) X/Y Memory Address Register Name Function Peripheral Name 0x3854 PMSA1 PMT status address register 1 PMT ch1 0x3855 PMS1 PMT size register 1 0x3856 PMC1 PMT control register 1 0x3857 PMP1 PMT address pointer 1...
Page 129 CHAPTER 5 PERIPHERALS Table 5-1. Memory Mapping of Peripheral Registers (3/3) X/Y Memory Address Register Name Function Peripheral Name 0x3883 ICR3 Interrupt control register 3 INTC 0x3884 ICR4 Interrupt control register 4 0x3885 ICR5 Interrupt control register 5 0x3886 ICR6 Interrupt control register 6 0x3887 ICR7...
Page 130: Time Division Multiplexing (Tdm) Serial Interface (Tsio)
CHAPTER 5 PERIPHERALS Time Division Multiplexing (TDM) Serial Interface (TSIO) The TDM serial interface (TSIO) is not only a standard mode serial interface that can be directly connected to a standard speech codec; it also includes a time division multiplexing mode serial transfer function that can be set for up to 128 slots.
Page 131: Tdm Serial Interface Pins
CHAPTER 5 PERIPHERALS Table 5-2. TDM Serial Interface Registers X/Y Memory Address Register Name Function Load/store 0x3800 TSDT TDM serial data register 0x3801 SST1 Serial status register 1 0x3802 TSST TDM serial status register 0x3803 TFMT TDM format register 0x3804 TTXL TDM transmit slot register (lower) 0x3805...
Page 132: Tdm Serial Interface Registers
CHAPTER 5 PERIPHERALS 5.3.2 TDM serial interface registers (1) TSDT (TDM serial data transfer register) TSDT is a 16-bit register that is used for input and output of TDM serial data. It includes separate registers for input and output. SDT(out) is a 16-bit register that sets data to be output. When a store instruction is executed to TSDT, data is input to this register from the peripheral bus.
Page 133 CHAPTER 5 PERIPHERALS (7) SOS (serial output shift register) SOS is a 16-bit shift register that shifts TDM serial data while outputting it from the TSO pin. When the specified number of bits have been output, new data is input from TSDT. SOS is not connected to the peripheral bus.
Page 134 CHAPTER 5 PERIPHERALS Table 5-4. Bit Configuration of SST1 (1/2) Name Function Load/Store SOTF Serial output transfer format setting bit • 0: Serial output with MSB first (default) • 1: Serial output with LSB first SITF Serial input transfer format setting bit •...
Page 135 CHAPTER 5 PERIPHERALS Table 5-4. Bit Configuration of SST1 (2/2) Name Function Load/Store Note SIRST Serial input reset enable bit This resets the serial input circuit. Afterward, SLER = 0 and SLEF = 0. This bit is automatically cleared to zero after serial input is reset. •...
Page 136: Timing Of Tdm Serial Interface
CHAPTER 5 PERIPHERALS Table 5-6. Bit Configuration of TFMT Name Function Load/Store 15 to 13 SRTX Transmit slot position setting bit • 000: Slots 0 to 31 (default) • 001: Slots 16 to 47 • 010: Slots 32 to 63 •...
Page 137 CHAPTER 5 PERIPHERALS Figure 5-3. Slots DSP #0 DSP #1 DSP #2 DSP #3 Transmit flag Transmit flag Transmit flag Transmit flag Receive flag Receive flag Receive flag Receive flag Serial Slot 0 Slot 1 Slot 2 Slot 3 Slot 31 Slot 0 Slot 1 ¥...
Page 138 CHAPTER 5 PERIPHERALS The slots from which data will be read and the slots to which data will be written can be defined by setting the respective 32-bit transmit and receive flags. In addition, multiple flags can be set. Data can be read from or transferred to the slots for which a flag has been set.
Page 139: Audio Serial Interface (Asio)
CHAPTER 5 PERIPHERALS Thus, there are four types of timing for the combinations described above. In part (a) of Figure 5-5, data starts at the frame’s next clock and there is no dummy bit. In part (b), data starts at the frame’s next clock and a one-bit dummy bit is inserted.
Page 140 CHAPTER 5 PERIPHERALS Figure 5-6. Block Diagram of Audio Serial Interface Peripheral bus ASI INT ASO INT Standard serial interface Audio serial interface ASDT(in) ASDT(out) ASST SDT (in) SDT(out) ASOS ASIS Note ASOEN /LRCLK Note ASIEN /MCLK Divider Note ASCK /BCLK Note This pin is used during standard serial interface mode.
Page 141: Audio Serial Interface Pins
CHAPTER 5 PERIPHERALS 5.4.1 Audio serial interface pins (1) BCLK (serial bit clock − − − − I/O) This clock pin is used for audio serial data input and output. Is it used for output during master mode and for input (default) during slave mode.
Page 142: Audio Serial Interface Registers
CHAPTER 5 PERIPHERALS 5.4.2 Audio serial interface registers (1) ASDT (audio serial data transfer register) ASDT is a 64-bit register that is used to input and output audio serial data. It includes separate registers for output and input. SDT (out) is a 64-bit register that sets data to be output. When a store instruction is executed to ASDT, data is input to SDT (out) from the peripheral bus.
Page 143 CHAPTER 5 PERIPHERALS Table 5-8. Bit Configuration of ASST (1/2) Name Function Load/Store SOAD Standard/audio serial interface selection bit • 0: Standard serial • 1: Audio serial (default) ASOEN Audio serial output use enable/disable bit • 0: Output use disable (default) •...
Page 144 CHAPTER 5 PERIPHERALS Table 5-8. Bit Configuration of ASST (2/2) Name Function Load/Store Note MSSEL Audio serial clock mode setting bit • 0: Master mode • 1: Slave mode (default) ASSER ASDT store error flag • 0: No error (default) •...
Page 145: Timing Of Audio Serial Interface
CHAPTER 5 PERIPHERALS 5.4.3 Timing of audio serial interface Figure 5-7 shows the audio serial interface’s output timing. Figure 5-7. Output Timing of Audio Serial Interface System clock Store instruction to ASDT interrupt request ASDT Data stored to ASDT ASSEF BCLK Data stored to ASDT is shifted ASOS...
Page 146 CHAPTER 5 PERIPHERALS Figure 5-8. Input Timing of Audio Serial Interface System clock Load instruction from ASDT interrupt request Data input from ASI ASDT ASLEF BCLK LRCLK First Second Last – 1 Last ASI (ASIS) When data is stored in ASDT twice in the 32-bit mode or four times in the 64-bit mode, the interrupt and load enable flag becomes inactive.
Page 147: Precautions On Asio During Startup
CHAPTER 5 PERIPHERALS 5.4.4 Precautions on ASIO during startup When starting the ASIO operation after the µ PD77210 Family has been started, the ASO pin outputs undefined data that is not anticipated. This is because the ASOS register is not initialized immediately after the power is applied and the contents of the register become undefined.
Page 148: Standard Serial Interface (Sio)
CHAPTER 5 PERIPHERALS Standard Serial Interface (SIO) The standard serial interface (SIO) is a serial interface that is compatible with conventional µ PD7701x Family and µ PD77111 Family devices. This mode can be set by switching the audio serial interface setting or TDM serial interface setting.
Page 149: Standard Serial Interface Pins
CHAPTER 5 PERIPHERALS 5.5.1 Standard serial interface pins (1) TSCK/ASCK (serial clock − − − − input) This clock pin is used for standard serial data input and output. Input and output of serial data and output and sampling of various serial interface signals are performed in synchronization with the TSCK signal.
Page 150: Standard Serial Interface Registers
CHAPTER 5 PERIPHERALS 5.5.2 Standard serial interface registers (1) SDT (serial data transfer register) SDT is a 16-bit register that is used for input and output of standard serial data. It includes separate registers for output and input. SDT(out) is a 16-bit register that sets data to be output. When a store instruction is executed to SDT, data is input to SDT(out) from the peripheral bus.
Page 151 CHAPTER 5 PERIPHERALS Table 5-10. Bit Configuration of SST (1/2) Name Function Load/Store SOTF Serial output transfer format setting bit • 0: Serial output with MSB first (default) • 1: Serial output with LSB first SITF Serial input transfer format setting bit •...
Page 152 CHAPTER 5 PERIPHERALS Table 5-10. Bit Configuration of SST (2/2) Name Function Load/Store Note SORST Serial output reset enable bit This resets the serial output circuit. Afterward, SSER = 0 and SSEF = 1. This bit is automatically cleared to zero after serial output is reset. •...
Page 153: Timing Of Serial Interface
CHAPTER 5 PERIPHERALS 5.5.3 Timing of serial interface (1) Serial output timing Generally, serial output is performed in the following steps. Operations in steps <1> through <6> without SDT store wait cycles are illustrated in Figure 3-49 (a) and (b) for continuous and non-continuous data, respectively.
Page 154 CHAPTER 5 PERIPHERALS Figure 5-11. Serial Interface Output Timing (a) Continuous data <4> (c) <4> (c) TSCK/ASCK (input) <4> (b) <4> (b) <4> (a) TSOEN/ASOEN (input) <3> <3> TSORQ (output) <5> (a) <5> (a) SSEF (status) <2> <2> <4> (d) <4>...
Page 155 CHAPTER 5 PERIPHERALS (2) Timing of serial input Generally, serial input is performed in the following steps. Operations in steps <1> through <4> without SDT load wait cycles are illustrated in Figure 5-12. <1> Serial data input sequence is started when an external device makes the serial input enable pin (TSIEN/ASIEN) active (high level) with the serial input enable (TSIAK) pin being active (high level).
Page 156 CHAPTER 5 PERIPHERALS Figure 5-12. Serial Interface Input Timing (a) SICM = 1, SIEF = 0; Continuous mode TSCK/ASCK (i nput ) <2> (a) <2> (c) <3> (b) <1> TSIEN/ASIEN (i nput ) <3> (a) TSIAK (o utput ) <2> (b) SLEF (status) <4>...
Page 157 CHAPTER 5 PERIPHERALS (3) I/O timing of non-standard serial clock Figure 5-13 shows the operation of the serial clock counter which are caused by non-standard serial clock. Data can be input/output even when TSIEN/ASIEN and TSOEN/ASOEN are active. If a bit shift occurs, however, the I/O timing cannot be corrected because a non-standard serial clock is input.
Page 158 CHAPTER 5 PERIPHERALS (4) Handshake There are three means to handshake with the serial interface of the µ PD77210 Family, which can be implemented by application programs: • Polling • Wait • Interrupt (a) Polling Synchronization of handshaking is established by always monitoring and evaluating the SDT store enable flag (SSEF) and SDT load enable flag (SLEF) of the serial status register (SST).
Page 159 CHAPTER 5 PERIPHERALS (b) Wait Under the following conditions, execution of data exchanges with the SDT (in) and/or SDT (out) registers cause instruction wait cycles: • When the store wait function is enabled (SSWE = 1) and a store to SDT (out) for serial output is to be executed, while SSEF = 0 (valid data exists in SDT (out)).
Page 160 CHAPTER 5 PERIPHERALS (c) Interrupt Handshaking is established by interrupts, if data can be stored to SDT(out) and data can be loaded from SDT(in). Therefore, the advantage of this format is that, even while other processing is under execution, serial I/O can be executed independently (asynchronously) of the processing. Here is an example of serial I/O using an interrupt: /* definition of serial I/O register names #define SST1...
Page 161: Precautions On Sio During Startup
CHAPTER 5 PERIPHERALS Caution Note the following points when executing serial output interrupt because the interrupt occurs after data has been transferred from the SDT register to the serial output shift register: (1) Transfer first dummy data and then forcibly generate an interrupt, or do not use interrupts during the transfer of the first data, depending on the interrupt mode.
Page 162: Host Interface (Hio)
CHAPTER 5 PERIPHERALS Host Interface (HIO) The host interface (HIO) is an interface circuit that is used to transfer data to and from an external host CPU. The HIO’s main features are as follows. • Bus width Byte (8-bit) mode: Addresses for either the higher 8 bits or the lower 8 bits of the host interface register (HDT) are selected for external access via an 8-bit external bus.
Page 163: Host Interface Pins
CHAPTER 5 PERIPHERALS 5.6.1 Host interface pins (1) HCS (host interface select − − − − I/O) This pin is used for input and output of host interface select signals. This pins is asserted active (low level) while the host is accessing the host interface registers. (2) HA0 and HA1 (host address −...
Page 164: Host Interface Registers
CHAPTER 5 PERIPHERALS 5.6.2 Host interface registers (1) HDT (host data transfer register) This 16-bit register is used to input or output host data from the host interface. It includes separate registers for input and output. HDT (out) is a 16-bit register that sets data to be output. When a store instruction is executed to HDT, data is input to this register from the peripheral bus.
Page 165 CHAPTER 5 PERIPHERALS Table 5-13. Bit Configuration of HST (2/2) Name Function Load/Store Read/Write (from DSP) (from host) HRER Host read error flag • 0: No error (default) • 1: Error This bit is set (= 1) when HREF = 0 and the CPU has read HDT. Once set, this bit does not change until a µ...
Page 166: Host Interface Registers From Perspective Of Host
CHAPTER 5 PERIPHERALS 5.6.3 Host interface registers from perspective of host The host CPU uses the HA0 and HA1 pins in the µ PD77210 Family device to specify which registers will be accessed. Table 5-14 shows the host interface registers used during access from an external device. Table 5-14.
Page 167: Timing Of Host Interface
CHAPTER 5 PERIPHERALS 5.6.4 Timing of host interface (1) Host read operation ( µ µ µ µ PD77210 Family → → → → host) Data is transferred from the µ PD77210 Family to the host in the following steps. Figure 5-15 shows reading operations of 16-bit data to HDT without wait cycles.
Page 168 CHAPTER 5 PERIPHERALS (2) Host write operation ( µ µ µ µ PD77210 Family ← ← ← ← host) Data is transferred from the host to the µ PD77210 Family in the following steps. Figure 5-16 shows examples of writing HDT without wait cycles when 16-bit data is transferred. <1>...
Page 169 CHAPTER 5 PERIPHERALS (3) Handshake Handshaking between the µ PD77210 Family and host can be established by: • Polling • Wait • Interrupt (a) Polling Synchronization of handshaking is established by always monitoring and evaluating the host read enable flag (HREF) and host write enable flag (HWEF) of the host interface status register (HST). Here is an example of host read ( µ...
Page 170 CHAPTER 5 PERIPHERALS (b) Wait Under the following conditions, execution of data exchanges with the HDT (in) and/or HDT (out) registers cause instruction wait cycles: • When the load/store wait function is enabled (HAWE=1) and a store to HDT (out) is to be executed, while HREF=1 (valid data exists in HDT (out)) •...
Page 171 CHAPTER 5 PERIPHERALS (c) Interrupts Handshaking can be established by generating an interrupt, if data can be stored to HDT(out) or loaded from HDT(in) by the µ PD77210 Family. Therefore, the advantage of this format is that host input/output can be executed independently (asynchronously) of the other processing even while other processing is under execution.
Page 172: External Data Memory Interface (Mio)
CHAPTER 5 PERIPHERALS Caution Because the host output interrupt occurs at the rising edge of the HRD pin when the higher byte of the HDT register is accessed, the following points must be noted. (1) Transfer the first data by forcibly generating an interrupt by transferring dummy data or by transferring data without using an interrupt, depending on the interrupt mode.
Page 173 CHAPTER 5 PERIPHERALS Figure 5-17. Block Diagram of External Data Memory Interface Peripheral bus DMA MIO MIO controller MADRHI MADPI MOFSI MCST MWAIT MADRLI MALPI MLENI MSHW MADRHO MADPO MOFSO Direct MIO MADRLO MALPO MLENO MIDX MD0 to MD15 MA0 to MA19 MHOLDRQ MHOLDAK MBSTB...
Page 174: Memory Interface Pins
CHAPTER 5 PERIPHERALS 5.7.1 Memory interface pins (1) MA0 to MA19 (memory address − − − − output) These are 20-bit memory address pins. They become high impedance when the bus is released. (2) MD0 to MD15 (memory data − − − − I/O) These are 16-bit data I/O pins.
Page 175 CHAPTER 5 PERIPHERALS • The number of hold cycles cannot be controlled (it is fixed at zero cycles) for memory read operations by the µ PD77213. • Neither the setup cycles nor the hold cycles can be controlled (they are fixed at zero cycles) for memory read operations by the µ...
Page 176 CHAPTER 5 PERIPHERALS (9) MADP (DMA access data address register) MADP is a 20-bit register that is used to indicate addresses during DMA access. It includes separate input and output registers. MADPI is the address register for input and MADPO is the address register for output. The value of MDAR is transferred to MADP when a store instruction to MCST is executed.
Page 177 CHAPTER 5 PERIPHERALS Table 5-16. Bit Configuration of MSHW Name Function Load/Store 15 and 14 Dside D side (0xC0000 to 0xFFFFF) access setup cycles • 0x0: 0 cycles • 0x1: 1 cycle • 0x2: 2 cycles • 0x3: 3 cycles (default) 13 and 12 D side (0xC0000 to 0xFFFFF) access hold cycles •...
Page 178 CHAPTER 5 PERIPHERALS Table 5-17. Bit Configuration of MWAIT Name Function Load/Store 15 to 12 Dside D side (0xC0000 to 0xFFFFF) access wait cycles • 0x0: 0 cycles • 0x1: 1 cycle • 0x2: 2 cycles • 0x3: 3 cycles •...
Page 179 CHAPTER 5 PERIPHERALS Table 5-18. Bit Configuration of MCST Name Function Load/Store Input MADP set request flag • 0: No request (default) • 1: Request sent When the value is 1, the contents of MADRLI and MADRHI are transferred to MADPI. After transfer is executed, the value becomes 0.
Page 180: Direct Access
CHAPTER 5 PERIPHERALS 5.7.3 Direct access This is a method for directly accessing the external data memory via an external data memory access window. The external data memory access window is assigned to the range of 0x8000 to 0xFFFF in either X or Y data memory when the DPR is 0x3F.
Page 181: Dma Access
CHAPTER 5 PERIPHERALS 5.7.4 DMA access This is a method for accessing external data memory via a memory mapped MDT (memory data register). The MADP value set by MADR is used as the address for accessing external data memory. MADR is a register that indicates the start address for DMA transfer, and when the corresponding bits in MCST are set, the transfer from MADR to MADP is executed.
Page 182 CHAPTER 5 PERIPHERALS Figure 5-19. DMA Access (a) Zero-dimensional Internal data memory External data memory (PMT) ¥ ¥ ¥ ¥ (b) One-dimensional (c) Two-dimensional Internal data memory Internal data memory External data memory External data memory (PMT) (PMT) 1 line length ¥...
Page 183: Direct Access Timing
CHAPTER 5 PERIPHERALS 5.7.5 Direct access timing Figure 5-20 shows the direct access timing. Figure 5-20. Direct Access Timing 0, 1 wait write (wait)+ 2 wait write MWAIT + 2 wait read System clock (Instruction) store to memory memory memory MIDX write read...
Page 184: Dma Access Timing
CHAPTER 5 PERIPHERALS 5.7.6 DMA access timing Figure 5-21 shows the DMA access timing. Figure 5-21. DMA Access Timing 0 wait write (wait)+ 2 wait write MWAIT + 2 wait read 0 wait read System clock (Instruction) store to memory store to memory memory...
Page 185: Timing Of Memory Access
CHAPTER 5 PERIPHERALS 5.7.7 Timing of memory access Figure 5-22 shows the memory access timing. Figure 5-22. Memory Access Timing Read (7 wait) Write (7 wait) System clock (Wait counter) (Set-up counter) (Hold counter) µ Remark MRD can be used for setup control of the PD77213 only. The memory write strobe (MWR) is needed to ensure the setup/hold period due to the risk of write errors to the address bus (MADD) and the memory data bus (MD).
Page 186 CHAPTER 5 PERIPHERALS The following describes wait insertion and operation using the external MWAIT pin. After the falling edge of the MRD and MWR pins, the MWAIT pin is asserted active (low level) and the signal used for this synchronization stops the updating of the programmable wait counter.
Page 187: Peripheral ↔ ↔ Memory Transfer (Pmt)
CHAPTER 5 PERIPHERALS Peripheral ↔ ↔ ↔ ↔ Memory Transfer (PMT) The peripheral ↔ memory transfer (PMT) controller is a DMA controller that transfers data from four peripheral circuits (TSIO, ASIO, HIO, and MIO) directly to the µ PD77210 Family device’s internal memory. There are eight channels in all: four each for input and output.
Page 188 CHAPTER 5 PERIPHERALS Table 5-19. PMT Registers X/Y Memory Address Register Name Function Load/Store 0x3850 PMSA0 PMT start address register 0 0x3851 PMS0 PMT size register 0 0x3852 PMC0 PMT control register 0 0x3853 PMP0 PMT address pointer 0 0x3854 PMSA1 PMT start address register 1 0x3855...
Page 189: Pmt Registers
CHAPTER 5 PERIPHERALS Table 5-20. PMT Transfer Channels and Target Peripherals PMT Channel Target Peripheral Transfer Direction Peripheral → memory TDM serial interface (input) Memory → peripheral TDM serial interface (output) Peripheral → memory Audio serial interface (input) Memory → peripheral Audio serial interface (output) Peripheral →...
Page 190 CHAPTER 5 PERIPHERALS Table 5-21. Bit Configuration of PMC Name Function Load/Store − 15 to 7 Reserved Values other than 0 cannot be written. • Undefined during a read operation Transfer monitor flag • 0: Transfer in progress (or initial status) •...
Page 191: Pmt Operation Modes
CHAPTER 5 PERIPHERALS 5.8.2 PMT operation modes PMT specifies the start address and buffer size (see Figure 5-26). When the operation is started, if it is an input operation, data sent from the peripheral is stored beginning at the start address, and if it is an output operation, data is read beginning from the start address and is sent to the peripheral.
Page 192: Pmt Transfer Steps
CHAPTER 5 PERIPHERALS 5.8.3 PMT transfer steps (1) The start address of the RAM area to be accessed is set to the PMSA register. Although this value can be changed during the PMT operation, the newly set value does not take effect until the next transfer operation starts.
Page 193: General-Purpose I/O Port (Pio)
CHAPTER 5 PERIPHERALS General-Purpose I/O Port (PIO) The general-purpose I/O port is a 4-bit port used for input and output. In µ PD77210 Family devices, four sets (P0 to P3, P4 to P7, P8 to P11, and P12 to P15) are included so that the entire group can be used as a 16-bit port. The following description uses P0 to P3 as an example, but the same configuration applies to the other general-purpose I/O ports as well.
Page 194: General-Purpose I/O Port Registers
CHAPTER 5 PERIPHERALS 5.9.2 General-purpose I/O port registers (1) PDT0 to PDT3 (port data transfer registers) These are 16-bit registers used for input and output of data via the general-purpose I/O port (only the lower four bits are valid). One register is allocated to each set of four general-purpose I/O port pins, and thus there are four registers (PDT0 to PDT3).
Page 195 CHAPTER 5 PERIPHERALS Table 5-23. Bit Configuration of PCD (2/2) Name Type Bit’s Function Load/Store (L/S) Mode setting I/O specification bit • 0: Specifies input port • 1: Specifies output port • The port setting is specified by M3 to M0. •...
Page 196: Timing Of General-Purpose I/O Port
CHAPTER 5 PERIPHERALS 5.9.3 Timing of general-purpose I/O port The general-purpose I/O port is not assumed to be used synchronously, but is synchronized with the rising edge of CLKOUT during data input/output. (1) Mode change from input to output System clock Instruction Store to PCD: input output...
Page 197: Example Program
CHAPTER 5 PERIPHERALS (2) Mode change from output to input System clock Instruction Store to PCD: output input Required 4 instruction cycles Load from PDT (for input data 1) Input/output mode Output Input Delay Input Input Input ···································· P0 to P3 Output data data 1 data 2...
Page 198 CHAPTER 5 PERIPHERALS (4) Timing of output ports System clock Instruction Store to PDT Store to PCD (bit manipulation) PDT (out) Data stored to PDT Bit manipulated data Delay Delay P0 to P3 Data stored to PDT Bit manipulated data (a) In case of store to PDT register The output data is output after one system clock since execution cycle of store to PDT register.
Page 199 CHAPTER 5 PERIPHERALS (5) Output port setting (by use of PCD and PDT registers) System clock Instruction Store to PCD: bit manipulation Store to PDT: output data Output Input/output mode Input Bit manipulation New manipulated data Old data New data Old data PDT (out) Delay...
Page 200: Example Of Port Programming
CHAPTER 5 PERIPHERALS 5.9.4 Example of port programming Here is an example of a program using the general-purpose input/output port. In this example, the following is executed: • P0 and P1 are set in the output mode. • P2 and P3 are set in the input mode. •...
Page 201: Interrupt Controller (Intc)
CHAPTER 5 PERIPHERALS 5.10 Interrupt Controller (INTC) Twelve interrupt ports are provided in the DSP core kernel. The interrupt controller (INTC) expands these 12 interrupt ports by allocating four interrupt factors (sources) to each port to enable interrupt handling for up to 48 factors. Table 5-24 lists the interrupt controller’s registers.
Page 202: Interrupt Controller's Registers
CHAPTER 5 PERIPHERALS 5.10.1 Interrupt controller’s registers (1) ICR0 to ICR11 (interrupt control registers) These are 16-bit registers that are used to set the interrupt mode and interrupt masking. One of these registers exists for each of the DSP core kernel’s interrupt ports (each interrupt vector address). Table 5-25 lists the functions of each bit in ICR.
Page 203: Operation Modes Of Interrupt Controller
CHAPTER 5 PERIPHERALS 5.10.2 Operation modes of interrupt controller When in stamp mode (IMODE = 1), the DSP core kernel’s interrupt ports are in factor expansion operation mode (see Figure 5-28). Figure 5-28. Interrupt Controller in Stamp Mode IMODE = 1 Factor 3 ×...
Page 204: Interrupt Table
CHAPTER 5 PERIPHERALS Figure 5-29. Interrupt Controller in Mask Mode IMODE = 0 Factor 3 × Factor 2 × Latch Interrupt Factor 1 × Factor 0 × ICR registers Peripheral bus For interrupt factors that have not been set as masked in the ICR, the ORed result is taken to issue an interrupt signal to the DSP core kernel.
Page 205: Hardware Conditions During Interrupt From External Interrupt Pins
CHAPTER 5 PERIPHERALS Table 5-26. Interrupt Table Interrupt Vector Interrupt Factor (Source) Number Address RESET 0x200 Reset Reserved Reserved Reserved 0x210 INT00 INT01 INT02 INT03 0x214 INT10 INT11 INT12 INT13 0x218 INT20 INT21 INT22 INT23 0x21C INT30 INT31 INT32 INT33 Note 0x220 TSI input...
Page 206: Interrupt-Related Precautions
CHAPTER 5 PERIPHERALS 5.10.5 Interrupt-related precautions (1) SR register and ICR register There are two types of interrupt mask flags. The relationship between the two types is shown in Figure 5-31. Figure 5-31. Relationship Between Two Types of Mask Flags Interrupt controller (INTC) DSP core kernel ICR register’s...
Page 207 CHAPTER 5 PERIPHERALS (2) fint instruction If an interrupt is input while global or specific interrupts are disabled, there is no actual branching to interrupt servicing since interrupts are disabled, but each interrupt factor is nevertheless recorded as an interrupt by the DSP core kernel.
Page 208 CHAPTER 5 PERIPHERALS (3) Sequence of setting interrupt enabled and interrupt disabled modes Enabled/disabled status can be set for each interrupt factor via the SR register and ICR register (see 5.10.5 (1) SR register and ICR register). Ultimately, both must be set to interrupt enable in order to enable interrupts, and the following describes the sequence of these settings.
Page 209: Timer (Tim)
CHAPTER 5 PERIPHERALS • Mask mode During mask mode, an interrupt signal that is input to the interrupt controller while the mask flag is cleared is input as is to the DSP core kernel. If the interrupt mask flag is cleared while in mask mode, the interrupt controller outputs a low level at the time when the mask flag is cleared in order to retain low level for Note Note...
Page 210: Timer Pins
CHAPTER 5 PERIPHERALS Figure 5-33 shows a block diagram of the timer and Table 5-27 lists its registers. Figure 5-33. Block Diagram of Timer (1 Channel) Peripheral bus Note INT (TIMOUT Controller TCSR Prescaler System clock TIN_1 TIN_2 TIN_3 TIN_4 Note TIMOUT pin exists only for ch0.
Page 211 CHAPTER 5 PERIPHERALS (2) TCR0 and TCR1 (timer count registers) These are 16-bit registers that are used to retain the current timer count value. This value is decremented during a timer count operation. The default value is 0xFFFF. When using the timer as a watchdog timer, be sure to store a value matching the TIR value before reaching time-up.
Page 212: Operation Of Timer
CHAPTER 5 PERIPHERALS Table 5-29. Timer Clock Sources (TCSR Bits 5 to 3) Bits 5 to 3 Clock Source 0 0 0 System clock System clock System clock 0 0 1 TIN_1 Serial clock for TSIO Serial clock for ASIO 0 1 0 TIN_2 P0 pin...
Page 213: Clock Controller (Clkc)
CHAPTER 5 PERIPHERALS 5.12 Clock Controller (CLKC) The clock controller controls clock signals input from an external clock input (CLKIN). It includes a PLL and an output divider. The PLL is used for frequency multiplication and the output divider for frequency division in order to generate the system clock.
Page 214: Clock Controller's Register
CHAPTER 5 PERIPHERALS Table 5-30. Clock Controller’s Register X/Y Memory Address Register Name Function Load/Store 0x38B0 CLKC Clock control register 5.12.1 Clock controller’s register (1) CLKC (clock control register) This register is used to set parameters for the PLL and divider. It sets the PLL’s on/off mode, and selects the clock source, the divider’s division rate, and the CLKOUT pin setting.
Page 215 CHAPTER 5 PERIPHERALS Table 5-31. Bit Configuration of CLKC (2/2) Name Function Load/Store 3 to 0 ODIV Division rate setting bit • 0000: 1/16 (default) • 0001: 1/1 • 0010: 1/2 • 0011: 1/3 • 0100: 1/4 • 0101: 1/5 •...
Page 216: Timing Of Clock Switching
CHAPTER 5 PERIPHERALS 5.12.2 Timing of clock switching When the system clock is switched, a regulating clock that has a longer high level width than before or after switching is inserted. Figure 5-35 illustrates this. Figure 5-35. Timing of Clock Switching (a) External clock →...
Page 217: Precaution Points On Clock Control
CHAPTER 5 PERIPHERALS 5.12.3 Precaution points on clock control The following describes clock control-related caution points and likely errors. (1) Clock switching The clock signal input from the CLKIN pin can be supplied as the system clock, either directly or via the PLL circuit or the divider.
Page 218 CHAPTER 5 PERIPHERALS Figure 5-37. State Transitions During PLL Operations and Divider Operations Reset <RESET> <BOOT> <STOP DIVIDER> PLL: “Undefined” “Stop” PLL: “×M” “Stop” DIV: “1/1(N)” “Stop” DIV: “1/16” “Stop” DIV: “1/1” “Operate” <START PLL> <SET DIVISION RATE> PLL: “×M” “Operate” DIV: “1/N”...
Page 219 CHAPTER 5 PERIPHERALS Figure 5-38. Example of PLL Settings Start PLL circuit clr (r0) r0l = *CLKC:x r0 = r0 | 0x0100 *CLKC:x = r0l Select PLL output clock (PLL circuit must have been started and PLL must be in lock mode) clr (r0) r0l = *CLKC:x r0 = r0 | 0x0180...
Page 220 CHAPTER 5 PERIPHERALS (2) Clock during standby mode When in standby mode (HALT/STOP), the divider’s output clock is selected automatically. Therefore, be sure to start the divider before using standby mode. When using HALT mode while the divider output clock is operating, the divider output clock will remain as it is, the clock is not switched.
Page 221: Instruction Memory Correction Function (Imc)
CHAPTER 5 PERIPHERALS 5.13 Instruction Memory Correction Function (IMC) The instruction memory correction (IMC) function is used to fetch instruction memory by replacing it with data that has already been set. Since it is an instruction memory correction function, it is used when patching the contents of ROM in the µ PD77213, which is a mask ROM device.
Page 222: Operation Of Instruction Correction Function
CHAPTER 5 PERIPHERALS (4) CUIR0, CUIR1, CLIR0, and CLIR1 (correction instruction registers) These are 16-bit registers that are used to specify the instruction code to be corrected (by performing patch processing). Since the instruction memory has 32-bit width, these registers are provided in pairs: one (CUIR) for the higher 16 bits and one (CLIR) for the lower 16 bits.
Page 223: Registers For Paging Function
CHAPTER 5 PERIPHERALS 5.14.1 Registers for paging function (1) IPR (instruction page register) This is a 16-bit register that is used to specify instruction pages in the instruction paging area. The paging is specified in the lower 6 bits. The specifiable range is from 0x0 to 0x3F. The default value is 0x0. (2) DPR (data page register) This is a 16-bit register that is used to specify data pages in the data paging area.
Page 224: Peripheral Stop Mode
CHAPTER 5 PERIPHERALS 5.15 Peripheral STOP Mode Peripheral STOP mode enables the clocks supplied to TSIO, ASIO, MIO, and PMT to be stopped individually. This mode can therefore be used to reduce the power consumption of unused peripheral circuits. Table 5-36 lists the register used by peripheral STOP mode. Table 5-36.
Page 225: Operation Of Peripheral Stop Mode
CHAPTER 5 PERIPHERALS 5.15.2 Operation of peripheral STOP mode Among the settings in the POWC register, 0x387A is handled as a port control setting for PDT and 0x387B is handled likewise for PCD. Bit manipulation is performed after setting output mode. Figure 5-42 shows an example of settings.
Page 226: Debug Interface Pins
CHAPTER 5 PERIPHERALS 5.16.2 Debug interface pins Four pins and In-Circuit Emulation pin (TICE) and test pin (TRST) conforming to the recommendation are provided. • TCK (input): Test clock input pin. Input 0 when not used (conforms to recommendation). Caution Do not stop TCK while it is high. •...
Page 227: Debug Function (In-Circuit Emulator Function)
CHAPTER 5 PERIPHERALS 5.16.4 Debug function (in-circuit emulator function) The µ PD77210 Family is provided with debug monitoring functions using JTAG with a run-time program. These functions have the following features: • • • • Break function Break by fetch of specified instruction address •...
Page 228: Expansion Interfaces (Additional I/O)
CHAPTER 5 PERIPHERALS 5.17 Expansion Interfaces (Additional I/O) The following describes additional inputs and outputs for the expansion interfaces. These additional inputs and outputs are interfaced by the SD card interface. The various expansion interfaces are described below starting on the next page.
Page 229: Expansion Interface Register
CHAPTER 5 PERIPHERALS 5.17.1 Expansion interface register (1) APCR (additional peripheral control register) This register is used to control the enabled/disabled status of the expansion interfaces (additional peripheral blocks) and to set control of PMT requests. It can control up to four peripheral blocks. One pair of load/store interrupts can be controlled per block.
Page 230: Sd Card Interface (Sdcif)
CHAPTER 5 PERIPHERALS 5.18 SD Card Interface (SDCIF) The µ PD77213 includes an SD (secure digital) card interface (SDCIF). This interface is configured within the expansion interfaces. The SD card interface specification is based on SD Memory Card Specifications, Part 1 Physical Layer Specification, Version 1.0, March 2000.
Page 231: Sd Card Interface Pins
CHAPTER 5 PERIPHERALS Table 5-41. SD Card Interface Registers External Memory Address Register Name Function Load/Store 0xFC000 SDDR SD card data register 0xFC001 SDCMD_IDX SD card command index register 0xFC002 SDCMD_AGH SD card command argument register (H) 0xFC003 SDCMD_AGL SD card command argument register (L) 0xFC004 SDCTL SD card interface control register...
Page 232: Sd Card Interface Registers
CHAPTER 5 PERIPHERALS 5.18.2 SD card interface registers (1) SDDR (SD card data register) This is a 16-bit register that is used for input and output of the SD card’s serial data. It includes separate registers for output and input. The value of SDDR can be input and output via MIO. SDDR(out) is a 16-bit register that sets data to be output to the SD card.
Page 233 CHAPTER 5 PERIPHERALS (4) SDRPR (SD card interface response register) This register is used to retain response data that has been received from the SD card. It has an (8 × 16 bit) FIFO configuration. SDRPR includes eight separate registers (SDRPR7 to SDRPR0), and when SDMCD_IDX’s BSL bit is 1 (response bits: 136 bits), response data is retained sequentially starting from SDRPR7.
Page 234 CHAPTER 5 PERIPHERALS Table 5-42. Bit Configuration of SDCMD_IDX Name Function Load/Store − • Values other than 0 must not be written. Reserved • Undefined during a read operation 14 to 11 Data block range setting bits • 0000: 1 byte •...
Page 235 CHAPTER 5 PERIPHERALS Table 5-43. Bit Configuration of SDCTL (1/2) Name Function Load/Store ALLE This flag indicates the error status within all of the SDCIF (SD card interface). This flag is set to 1 when an error flag has been set in CRRE, CRDE, SDSE, or SDLE. •...
Page 236 CHAPTER 5 PERIPHERALS Table 5-43. Bit Configuration of SDCTL (2/2) Name Function Load/Store CRDE CRC data error flag The CRC result for the data received from the SD card is compared with the CRC result calculated within the µ PD77213, and if the two results do not match this bit (CRDE) is set (= 1).
Page 237: Crc (Cyclic Redundancy Codes) Circuit
CHAPTER 5 PERIPHERALS Table 5-44. Configuration of SDRPR Register Register Name Function SDRPR7 This register is used to retain responses in bits 127 to 112, out of bits 135 to 0 that have received responses from the SD card. The response in SDCSR are first retained, and after all valid responses have been retained in SDRPR, the first load operation can be performed for output via the MIO bus.
Page 238: Operation Of Sd Card Interface
CHAPTER 5 PERIPHERALS 5.18.4 Operation of SD card interface Access to the SD card is implemented using the registers that have been mapped to the external memory space via the MIO bus. Status-based polling and interrupts can be used for this access. Wait-based access cannot be used.
Page 239 CHAPTER 5 PERIPHERALS Table 5-45. Bit Configuration of µ µ µ µ PD77213’s APCR Register (2/2) Name Function Load/Store Peripheral B Not used (MIO) Set to 1. Not used Set to 0. Peripheral C Data store request interrupt enable flag (SDCIF) Enables data store request interrupt signal from SDCIF.
Page 240: Chapter 6 Boot Functions
CHAPTER 6 BOOT FUNCTIONS This chapter describes the boot functions in µ PD77210 Family devices. µ PD77210 Family devices include interrupt vectors and instruction memory RAM that begins at address 0x0200. Application programs must be loaded to this instruction RAM space. The boot routine that is used to boot instructions in the instruction RAM (part of the instruction memory space) is stored in ROM.
Page 241: Memory Boot
CHAPTER 6 BOOT FUNCTIONS Table 6-2. PLL’s Lock Range Lock Range 120 to 160 MHz 80 to 120 MHz Caution During boot processing, the general-purpose port settings should remain fixed from three cycles prior to system reset release to the instruction execution cycle at address 0x200 following operation of the boot program.
Page 242: Y Memory Boot
CHAPTER 6 BOOT FUNCTIONS 6.1.3 Y memory boot In this boot mode, instruction code is booted starting from address 0x8000 (DPR = 0x0) in internal Y data memory. The number of instruction steps to be booted and the source start address are required as parameters. The maximum number of boot words is 0x4000 (16 Kwords) –...
Page 243: Xy Memory Boot
CHAPTER 6 BOOT FUNCTIONS 6.1.4 XY memory boot In this boot mode, instruction code is booted starting from address 0x8000 (DPR = 0x0) in both internal X data memory and internal Y data memory. The higher 16 bits of the instruction code are booted from Y memory and the lower 16 bits are booted from X memory.
Page 244: External Data Memory Boot
CHAPTER 6 BOOT FUNCTIONS 6.1.5 External data memory boot In this boot mode, instruction code is booted from external data memory. The number of instruction steps to be booted and the source start address are required as parameters, along with the wait count. The maximum number of boot words is 0x4000 (16 Kwords).
Page 245: Host Boot
CHAPTER 6 BOOT FUNCTIONS 6.1.6 Host boot In host boot mode, the host device boots the instruction code from the host device via the host interface. The number of instruction steps to be booted and the HST (host status register) are required as parameters. The wait operation performs handshaking with the host interface.
Page 246 CHAPTER 6 BOOT FUNCTIONS (2) Host boot parameters The host boot parameters for a reset are described below. • No. of boot instructions: This indicates the number of instruction steps (number of boot-related instructions) in the boot program. The amount of data that is actually transferred as data is double the number of instruction steps.
Page 247: Serial Boot
CHAPTER 6 BOOT FUNCTIONS 6.1.7 Serial boot In this mode, instruction code is booted by a serial device working via the TDM serial interface. The number of instruction steps to be booted and the SST (serial status register) are required as parameters. The wait operation performs handshaking with the serial interface.
Page 248: Initial Reset Boot And Pll
CHAPTER 6 BOOT FUNCTIONS Initial Reset Boot and PLL The operation of the PLL differs depending on the initial reset boot mode. A reset forcibly sets operation based on an externally input clock. In some boot modes, the PLL is started by the boot routine.
Page 249: Reboot
CHAPTER 6 BOOT FUNCTIONS Reboot Reboot means that an application calls a reboot routine from ROM in order to enable setting of instruction data to instruction RAM. Table 6-4 lists reboot entry addresses and parameters for settings. For reboot, the transfer source and transfer destination pages can be specified. Also, during a reboot there is no distinction between instructions and data as objects to be transferred.
Page 250: Appendix A Index
APPENDIX A INDEX A.1 Terminology Index DMA access ............181 DSP core kernel............43 Accumulative multiplication function....... 117 Additional I/O............228 Address ALU ............97 EB................80 Addressing mode ............. 97 EI ................80 ALU operation function........... 121 EIR................82 Architecture ..............
Page 251 APPENDIX A INDEX Indirect addressing........... 99 ME ................194 Initial reset boot..........240, 248 MIO.................172 Instruction memory ..........61 Modifying data pointers ..........102 Instruction memory aliasing ........94 Modulo index addition and cyclic buffer ....103 Instruction memory correction function ....221 Multiple interrupts .............83 Instruction page register ........
Page 252 APPENDIX A INDEX Pre-bit reverse and post index addition ....101 Standby mode set by STOP instruction ....58 Precaution points on clock control......217 ste................89 Program control unit ..........59 System control unit ..........48 Program counter ............60 Program execution control block ......
Page 253: Register Index
APPENDIX A INDEX A.2 Register Index A.2.1 Register name order Additional peripheral control register: APCR......................229 Audio serial data transfer register: ASDT........................142 Audio serial status register: ASST ..........................142 Clock control register: CLKC............................214 Correction address registers: CAR0 and CAR1 ......................221 Correction enable flag register: CEFR ........................
Page 254 APPENDIX A INDEX MIO data transfer register: MDT..........................174 MIO direct access index register: MIDX ........................175 MIO line length register for input: MLENI........................175 MIO line length register for output: MLENO........................175 MIO line offset register for input: MOFSI ........................175 MIO line offset register for output: MOFSO ........................175 MIO setup hold width register: MSHW ........................174 MIO start address register for input (higher): MADRHI....................175 MIO start address register for input (lower): MADRLI....................175...
Page 255 APPENDIX A INDEX TDM frame format register: TFMT..........................132 TDM receive slot register (higher): TRXH ........................132 TDM receive slot register (lower): TRXL........................132 TDM serial data transfer register: TSDT........................132 TDM serial status register: TSST ..........................132 TDM transmit slot register (higher): TTXH........................132 TDM transmit slot register (lower): TTXL........................
Page 256: Register Symbol Order
APPENDIX A INDEX A.2.2 Register symbol order APCR: Additional peripheral control register ......................229 ASDT: Audio serial data transfer register ........................142 ASST: Audio serial status register ..........................142 CAR0 and CAR1: Correction address registers ......................221 CEFR: Correction enable flag register........................221 CLIR0 and CLIR1: Correction instruction registers (lower)..................222 CLKC: Clock control register ............................214 CPR0 and CPR1: Correction page registers ......................221 CUIR0 and CUIR1: Correction instruction registers (higher) ..................222...
Page 257 APPENDIX A INDEX MDT: MIO data transfer register..........................174 MIDX: MIO direct access index register ........................175 MLENI: MIO line length register for input ........................175 MLENO: MIO line length register for output ....................... 175 MOFSI: MIO line offset register for input........................175 MOFSO: MIO line offset register for output ........................
Page 258 APPENDIX A INDEX TRXH: TDM receive slot register (higher)........................132 TRXL: TDM receive slot register (lower)........................132 TSDT: TDM serial data transfer register ........................132 TSST: TDM serial status register..........................132 TTXH: TDM transmit slot register (higher) ........................132 TTXL: TDM transmit slot register (lower) ........................132 User’s Manual U15807EJ2V0UM...
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