IBM 7302 Manual Of Instruction page 29

. Assume a bit is in MAR positions A and C during the read portion of a core storage
cycle. Converter output lines A, B, C,
D,
and R have an up-level; lines
A:
B,
C,
D, and
R
are down. The converter output lines feed eight minus exclusive OR
circuits (-OE) and two converters. Figure
3. 3-5
illustrates characteristics of -OE
and +OE circuits.
~~dBAlike
~~dBLnl;k,
A r r a n d B Unlike
A
-OE
B
8 .
A and B Alike
A A
B B
l 0 l 0
0 l l 0
l 0 0 l
0 l
0
l
A
A
B
B
l 0 l 0
0
1-
l 0
l 0 0 1
0 l 0 l
Out-of- In-
Phase Phase
Ou!e_ut Output
l 0
0 l
0 l
l
0
Out-of- In-
Phase Phase
Ou~t
Ou_!E_ut
0
l
l 0
l 0
0 l
FIGURE 3. 3-5. EXCULSIVE OR CHARACTERISTICS
The symbol
'V'
means "exclusive OR;" therefore, R
'V'
A for an output means that
either input, R or A, is an up-level, but not both. The not function,
~indicates
that R and A or R and
A
both have
an
up-level on the input to the circuit,
The lines with an up-level to -OE
1
(Figure 32:.iLare A and R; therefore, the up-
level output is the in-phase output line marked R V A. On -OE2, the up-level is the
out-of-phase line marked R kt B because the up-level inputs are R and
B.
Similar
logic determines which line is up for the remaining -OE and C circuits.
At this point, the four
MAR
inputs and the read or write trigger output have been
expanded to ten complementary, or a total of 20, lines. The 20 lines, called first
level memory address drivers
(MAD),
are further combined through C's and +OE's
to develop
16
complementary lines or a total of 32 lines which condition core drivers
(DC) in each of the eight segments. The input to a core driver is an AND circuit;
one leg of the AND circuit is conditioned from the segment gating, the other from
address decoding.
Output lines to the core drivers are labeled so that the output lines with an up-
level can be determined from a knowledge of which
MAR
positions have a bit in them.
Using the previous example, where there was a bit in MAR positions A and C, check
the +OE feeding
C4.
The inputs to the +OE are an up-level R and
an
up-level A
>rt
B
from -OE
3 .
The up-level output of C4 is R
Jr/'
(A
Jr:/- B)
because both
R
and (A
'I(/'
B)
are up. The same conclusion could have been reached by considering only the
MAR
outputs. The original conditions gave us R;
(A
lrf
B)
requires that A or
B
be up, but
not both, which is the case; therefore, both Rand (A "'!
B)
are up-levels. The
notation R )(/"
(A
)if
B)
is used to denote that both
R
and
(A
lrf
B)
are up. This is
the same line that was developed using the inputs to the +OE circuit. Notice also
that when the core storage unit is in the write portion of the cycle, the complement
line out of C4 is up. In this case (A >rt-
B)
is an up-level, but R is a down-level;
therefore, R )(/"
(A
"1-
B)
is the line with the up-level. The same condition holds true
for all of the driver lines; one line is up during the read portion of the cycle and the
complement line is up during the write portion of the cycle.
It
is this reversal that
conditions the core drivers so X and Y drive line current is in one direction for a
read cycle and in the opposite direction for a write cycle.
F27