Ricoh RS5C372A Manual
Ricoh RS5C372A Manual

Ricoh RS5C372A Manual

I2c bus serial interface real-time clock ic

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2
I
C bus SERIAL INTERFACE REAL-TIME CLOCK IC
OUTLINE
The RS5C372A is a CMOS type real-time clock which is connected to the CPU via 2-wires and capable of
serial transmission of clock and calendar data to the CPU.
The RS5C372A can generate various periodic interrupt clock pulses lasting for long period (one month), and
alarm interrupt can be made by days of the week, hours, and minutes by two incorporated systems. Since an
oscillation circuit is driven at a constant voltage, it undergoes fluctuations of few voltage and consequently offers
low current consumption (Typ. 0.5μA at 3V). It also provides an oscillator halt sensing function applicable for data
validation at power-on and other occasions and 32-kHz clock output for an external micro computer. (Nch. open
drain output) The product also incorporates a time trimming circuit that adjusts the clock with higher precision
by adjusting any errors in crystal oscillator frequencies based on signals from the CPU. The crystal oscillator
may be selected from 32.768kHz or 32.000kHz types. Integrated into an ultra compact and ultra thin 8 pin SSOP
package, the RS5C372A is the optimum choice for equipment requiring small sized and low power consuming
products.
FEATURES
Time keeping voltage: 1.3V to 6.0V
Lowest supply current: 0.5μA Typ. (0.9μA Max.) : 3V (25°C)
Connected to the CPU via only 2−wires (I
A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years,
months, and days of the week) in BCD codes
Interrupt to the CPU (period of one month to one second, interrupt flag, interrupt halt
function)( INTRA , INTRB )
Two systems of alarm functions (days of the week, hours, and minutes) ( INTRA , INTRB )
Oscillation halt sensing to judge internal data validity
Clock output of 32.768kHz (32.000kHz) (output controllable via a register) ⋅⋅⋅ (Nch. open drain output)
Second digit adjustment by ±30 seconds
Automatic leap year recognition up to the year 2099
12-hour or 24-hour time display selectable
Oscillation stabilizing capacity (C
High precision time trimming circuit
Oscillator of 32.768kHz or 32.000kHz may be used
CMOS logic
Package: 8pin SSOP
(1.0μA Max.) : 3V (−40 to +85°C)
2
C bus Interface, Max.400kHz, address 7bit)
, C
) incorporated
G
D
RS5C372A/B
NO.EA-044-100928
1

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  • Page 1 NO.EA-044-100928 OUTLINE The RS5C372A is a CMOS type real-time clock which is connected to the CPU via 2-wires and capable of serial transmission of clock and calendar data to the CPU. The RS5C372A can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by days of the week, hours, and minutes by two incorporated systems.
  • Page 2: Block Diagram

    RS5C372A BLOCK DIAGRAM ALARM_A REGISTER COMPARATOR_A (WEEK,MIN,HOUR) 32kHz OUTPUT CONTROL ALARM_B REGISTER COMPARATOR_B (WEEK,MIN,HOUR) OSCIN DIVIDER TIME COUNTER CORREC (SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR) -TION OSCOUT ADDRESS ADDRESS DETECT DECODER REGISTER INTRA CONTROL INTRB INTERRUPT CONTROL SHIFT REGISTER APPLICATIONS • Communication devices (multi function phone, portable phone, PHS or pager) •...
  • Page 3: Pin Descriptions

    Oscillator Circuit 32.000kHz crystal oscillator between the OSCIN-OSCOUT pins. OSCOUT Input/Output (Any other oscillator circuit components are built into the RS5C372A.) Positive Power Supply Input The V pin is connected to the positive power supply and V Negative Power Supply Input to the ground.
  • Page 4: Recommended Operating Conditions

    RS5C372A RECOMMENDED OPERATING CONDITIONS (Vss=0V,Topt=−40 to +85°C) Symbol Item Conditions Min. Typ. Max. Unit Supply Voltage Timekeeping Voltage 32.768 Oscillation Frequency 32.000 Pull-up Voltage 1 SCL, SDA PUP1 Pull-up Voltage 2 10.0 INTRA , INTRB PUP2 DC CHARACTERISTICS =3V, Topt=−40 to +85°C, Oscillation frequency=32.768kHz, or 32.000kHz(R1=30kΩ)
  • Page 5 RS5C372A AC CHARACTERISTICS • ≥1.7V (supports standard mode I C bus) =0V, Topt=−40 to +85, Crystal=32.768kHz or 32.000kHz, Unless otherwise specified : V Input and Output Conditions:VIH=0.8×VDD,VIL=0.2×VDD,VOL=0.2×VDD,CL=50pF Symbol Item Conditions Min. Typ. Max. Unit SCL Clock Frequency μs SCL Clock “L” Time μs...
  • Page 6 RS5C372A • ≥2.5V (supports fast mode I C bus) =0V, Topt=−40 to +85, Crystal=32.768kHz or 32.000kHz, Unless otherwise specified : V Input and Output Conditions:VIH=0.8×VDD,VIL=0.2×VDD,VOL=0.2×VDD,CL=50pF Symbol Item Conditions Min. Typ. Max. Unit SCL Clock Frequency μs SCL Clock “L” Time μs...
  • Page 7 RS5C372B C bus SERIAL INTERFACE REAL-TIME CLOCK IC OUTLINE The RS5C372B is a CMOS type real-time clock which is connected to the CPU via 2-wires and capable of serial transmission of clock and calendar data to the CPU. The RS5C372B can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by days of the week, hours, and minutes by two incorporated systems.
  • Page 8 RS5C372B BLOCK DIAGRAM ALARM_A REGISTER COMPARATOR_A (WEEK,MIN,HOUR) 32kHz OUTPUT 32KOUT CONTROL ALARM_B REGISTER COMPARATOR_B (WEEK,MIN,HOUR) OSCIN DIVIDER TIME COUNTER CORREC (SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR) -TION OSCOUT ADDRESS ADDRESS DETECT DECODER REGISTER CONTROL INTR INTERRUPT CONTROL SHIFT REGISTER APPLICATIONS • Communication devices (multi function phone, portable phone, PHS or pager) •...
  • Page 9 32.768kHz or 32.000kHz crystal oscillator between the OSCIN OSCOUT Input/Output -OSCOUT pins. (Any other oscillator circuit components are built into the RS5C372A.) Positive Power Supply Input The V pin is connected to the positive power supply and V Negative Power Supply Input to the ground.
  • Page 10 RS5C372B RECOMMENDED OPERATING CONDITIONS (Vss=0V,Topt=−40 to +85°C) Symbol Item Conditions Min. Typ. Max. Unit Supply Voltage Timekeeping Voltage 1.45 32.768 Oscillation Frequency 32.000 Pull-up Voltage 1 SCL, SDA PUP1 Pull-up Voltage 2 10.0 INTR PUP2 DC CHARACTERISTICS =3V, Topt=−40 to +85°C, Oscillation frequency=32.768kHz, or 32.000kHz(R =30kΩ) Unless otherwise specified: Vss=0V, V Symbol...
  • Page 11 RS5C372B AC CHARACTERISTICS • ≥2.0V (supports standard mode I C bus) =0V, Topt=−40 to +85, Crystal=32.768kHz or 32.000kHz, Unless otherwise specified : V Input and Output Conditions:VIH=0.8×VDD,VIL=0.2×VDD,VOL=0.2×VDD,CL=50pF Symbol Item Conditions Min. Typ. Max. Unit SCL Clock Frequency μs SCL Clock “L” Time μs SCL Clock “H”...
  • Page 12 RS5C372B • ≥2.5V (supports fast mode I C bus) =0V, Topt=−40 to +85, Crystal=32.768kHz or 32.000kHz, Unless otherwise specified : V Input and Output Conditions:VIH=0.8×VDD,VIL=0.2×VDD,VOL=0.2×VDD,CL=50pF Symbol Item Conditions Min. Typ. Max. Unit SCL Clock Frequency μs SCL Clock “L” Time μs SCL Clock “H”...
  • Page 13: General Description

    ⋅ RS5C372A The RS5C372A has an alarm function that outputs an interrupt signal from INTRA or INTRB output pins to the CPU when the day of the week, hour or minute corresponds to the setting. These two systems of alarms (Alarm_A, Alarm_B), each may output interrupt signal separately at a specified time.
  • Page 14 The oscillation halt sensing function uses a register to store oscillation halt information. This function may be used to determine if the RS5C372A/B supply power has been booted from 0V and if it has been backed up. This function is useful for determining if clock data is valid or invalid.
  • Page 15: Table Of Contents

    ∗4) When XSTP is set to “1”, the XSL , F to F , CT to CT , AALE, BALE, SL , SL , CLEN and TEST bits are reset to “0”. ∗5) SL and SL apply to the RS5C372A. For the RS5C372B, these bits must be filled with “0”.
  • Page 16 ∗1) The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. ∗2) SL and SL apply to the RS5C372A. For the RS5C372B, these bits must be filled with “0”. 2.1-1 AALE, BALE Alarm_A, Alarm_B enable bits...
  • Page 17 RS5C372A/B 2.1-4 CT , CT , CT Periodic interrupt cycle select bit Description Wave Form Mode Cycle and Falling Timing — off (“H”) (Default) — Fixed at “L” Pulse Mode 2Hz (Duty50%) Pulse Mode 1Hz (Duty50%) Level Mode Every second (synchronized with second count up)
  • Page 18 RS5C372A/B • Level mode CTFG bit INTRA or INTRB pins (INTR pin for the RS5C372B) Write 0 to CTFG Write 0 to CTFG (Second count-up) (Second count-up) (Second count-up) 2.2 Control Register 2 (at internal address Fh) — — CTFG...
  • Page 19 32kHz clock pulses. ⋅ The XSTP bit is set to “0” by setting the control register 2 (address Fh) during ordinary oscillation. ∗) INTRA and INTRB for the RS5C372A, INTR and 32KOUT for the RS5C372B. 2.2-4 CLEN 32-kHz Clock Output Bit...
  • Page 20 RS5C372A/B 2.2-5 CTFG Periodic Interrupt Flag Bit CTFG Description (Default) Periodic interrupt output=OFF (“H”) Periodic interrupt output=ON (“L”) ∗ 1 This bit is set to “1” when periodic interrupt pulses are output ( INTRA or INTRB =“L”) The CTFG bit may be set only to “0” in the interrupt level mode. Setting this bit to “0” sets either the INTRA or ∗...
  • Page 21 RS5C372A/B 2.3 Clock Counter (at internal address 0-2h) ⋅ Time digit display (in BCD code) Second digits : Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits : Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
  • Page 22: Day Of The Week Counter

    RS5C372A/B 2.4 Day-of-the-week Counter (at internal address 3h) ⋅ Day-of-the-week digits are incremented by 1 when carried to 1-day digits. ⋅ Day-of-the-week digits display (incremented in septimal notation): )=(0,0,0) → (0,0,1) → ⋅⋅⋅⋅⋅ → (1,1,0) → (0,0,0) ⋅ The relation between days of the week and day-of-the-week digits is user changeable (e.g. Sunday=0,0,0).
  • Page 23: Time Trimming Register

    RS5C372A/B 2.5-3 Year digit register (at internal address 6h) (For write operation) (For read operation) ∗ Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default ∗)The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.
  • Page 24 RS5C372A/B 2.7 Alarm_A, Alarm_B Register (Alarm_A: internal address 8 to Ah; Alarm_B: internal address B to Dh) 2.7-1 Alarm_A minute register (internal address 8h) — (For write operation) (For read operation) ∗ Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default 2.7-2 Alarm_B minute register (internal address Bh)
  • Page 25 RS5C372A/B 2.7-6 Alarm_B day-of-the-week register (internal address Dh) — (For write operation) (For read operation) ∗ Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default ∗)The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.
  • Page 26 RS5C372A/B USAGES 1. Interfacing with the CPU The RS5C372A/B employ the I C bus system to be connected to the CPU via 2-wires. Connection and transfer system of I C bus are described in the following sections. 1.1 Connection of I...
  • Page 27 RS5C372A/B Cautions on Determining Rp Resistance (1) Voltage drop at Rp due to sum of input current or output current at off conditions on each IC pin connected to the I C bus shall be adequately small. (2) Rising time of each signal shall be kept short even when all capacity of the bus is driven.
  • Page 28 RS5C372A/B 1.2 Transmission System of I C bus 1.2-1 Start and stop conditions In I C bus, SDA must be kept at a certain state while SCL is at the “H” state as shown below during data transmission. or t The SCL and SDA pins are at the “H”...
  • Page 29 7bit address is sequentially transmitted from the MSB and 2 and after bytes are read, when 8bit is “H” and write when “L”. The slave address of the RS5C372A/B are specified at (0110010). At the end of data transmission/receiving stop condition is generated to complete transmission. However, if start condition is generated without generating stop condition, repeated start condition is met and transmission/receiving data may be continued by setting the slave address again.
  • Page 30 C bus standard defines a transmission format for the slave address allocated for each IC, transmission method of address information in IC is not defined. The RS5C372A/B transmit data the internal address pointer (4bit) and the transmission format register (4bit) at the 1byte next to one which transmitted a slave address and a write command.
  • Page 31 1.2-5 Data transmission read format of the RS5C372A/B The RS5C372A/B allow the following three readout methods of data from an internal register. 1) The first method to reading data from the internal register is to specify an internal address by setting the internal address pointer and the transmission format register described 1.2-4, generate the repeated start...
  • Page 32 RS5C372A/B 2) The second method to reading data from the internal register is to start reading immediately after writing to the internal address pointer and the transmission format register. Although this method is not based on the I bus standard in a strict sense it still effective to shorten read time to ease load to the master. Set 4h to the transmission format register when this method is used.
  • Page 33 RS5C372A/B 3) The third method to reading data from the internal register is to start reading immediately after writing to the slave address and the R/ W bit. Since the internal address pointer is set to Fh by default as described in 1), this method is only effective when reading is started from the internal address Fh.
  • Page 34 (from start condition to stop condition). When 0.5 to 1.0 second elapses after start condition any access to the RS5C372A/B are automatically released to release tentative hold of the clock, set Fh to the address pointer, and access from the CPU is forced to be terminated (the same action as made stop condition is received: automatic resume function from the I C bus interface).
  • Page 35 AC coupling : Permissible except that unpredictable results may occur in oscillator halt sensing due to possible sensing errors caused by noises, etc. 2) Avoid using the oscillator output of the RS5C372A/B (from the OSCOUT pin) to drive any other IC for the purpose of ensuring stable oscillation.
  • Page 36 2.3 Oscillation Frequency Adjustment Adjustment amount of oscillation frequency may differ dependent on how the RS5C372A/B is used or how much clock error is permissible in the system it is installed. Use the flow chart shown below find an optimal oscillation frequency adjustment method.
  • Page 37 Precision fluctuations of a crystal oscillator may be selected as long as clock precision allows. Obtain the central frequency as described in section 2.2 using several crystal oscillator and ICs, determine an adjustment value as described in “2.4 Time Trimming Circuit” which shall be set to the RS5C372A/B. (B) course To keep clock precision within the range of (fluctuation in crys-tal oscillator + fluctuation in IC), clock shall be adjustment is required for each IC.
  • Page 38 RS5C372A/B 2.4 Time Trimming Circuit Using the time trimming circuit gain or lose of clock may be adjusted with high precision by changing clock pulses for one second every 20 seconds. When adjustment with this circuit is not necessary, set (F ) to (∗, 0, 0, 0, 0, 0,∗) to disable adjustment.
  • Page 39 Time Trimming function. 1. Using Time Trimming function 2. Access to RS5C372A/B at random, or synchronized with external clock that has no relation to RS5C372A/B, or synchronized with periodic interrupt in pulse mode. 3. Access to RS5C372A/B more than 2 times per each second on average.
  • Page 40 Further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit. 4. INTRA Output and INTRB Output Pins (RS5C372A), INTR Output Pin (RS5C372B) 4.1 INTRA Output and INTRB Output Pins (RS5C372A) The following three output wave forms can be output from the INTRA or the INTRB pin.
  • Page 41: Alarm_A (Minute Register)

    RS5C372A/B 4.1-1 Control of the INTRA , INTRB Output (flag bit, enable bit, interrupt output select bit) (RS5C372A) Of the three output wave forms listed above, interrupt output conditions may be set by setting the flag bit that monitors output state on the register, the enable bit that enables an output wave form and the output select bit that selects either INTRA or INTRB to be output a wave form to.
  • Page 42 RS5C372A/B 4.1-2 Alarm Interrupt (RS5C372A) For setting an alarm time, designated time such as day-of-the-week, hour or minute should be set to the alarm registers being AALE (BALE) bit to 0. After that set the AALE (BALE) bit to 1, from this moment onward when such registered alarm time coincide the value of calendar counter the INTRA or INTRB comes down to “L”...
  • Page 43: Alarm_A (Hour Register)

    RS5C372A/B 4.2-1 Control of the INTR Output (flag bit, enable bit, interrupt output select bit) (RS5C372B) Of the two output wave forms listed above, interrupt output conditions may be set by setting the flag bit that monitors output state on the register, the enable bit that enables an output wave form.
  • Page 44 RS5C372A/B 4.3 Periodic (Clock) Interrupt The INTRA or INTRB pin ( INTR for the RS5C372B) output, the periodic interrupt cycle select bits (CT , CT ) and the interrupt output select bits (SL , SL ) can be used to interrupt the CPU in a certain cycle. The periodic interrupt cycle select bits can be used to select either one of two interrupt output modes: the pulse mode and the level mode.
  • Page 45 (Second count-up) (Second count-up) 4.4 32-kHz Clock Output ⋅ RS5C372A The crystal oscillator can generate clock pulses of 32kHz from the INTRB pin. The pin is changed to “H” by setting the CLEN bit to “1”. ∗1) 32-kHz clock output will not be affected from settings in the clock adjustment register.
  • Page 46 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Position A in the left figure (II) When in use during battery back-up ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Position B in the left figure *3) INTRA and INTRB for the RS5C372A, INTR for the RS5C372B. Example 2 System power supply *1) Connection in the example shown left...
  • Page 47 INTRB OSCIN 32.768kHz or OSCOUT 32.000kHz ∗) The SCL and SDA pins of the RS5C372A do not contain protective diodes on V side. Therefore, back up power supply≤system power supply causes no adverse effect. ⋅ RS5C372B System power supply Backup power supply...
  • Page 48 CE will not change to “H” while 32-kHz clock is off (“H”) to allow the regulator to be turned on. ∗3) This resistor is used to prevent excess current from flowing into the pins of the RS5C372A and the RN5RZ××A (RN5RT××A) on power on.
  • Page 49 OSCOUT Frequency INTRB (32KOUT) counter *1) INTRB applies to the RS5C372A, and the 32KOUT applies to the RS5C372B. The RS5C372B does not need pull up resistor. 6.1 Standby Supply Current vs. Power Supply 6.2 Supply Current During 32k Clock Output Voltage vs.
  • Page 50 RS5C372A/B 6.5 Standby Supply Current vs. Temperature 6.6 Oscillation Frequency Deviation vs. External C (Topt=25 =3V, =3.0V, SDA=Open) External C =0pF Standard) −10 −20 −30 −40 −50 −60 −40 −20 Temperature Topt( External C (pF) 6.7 Oscillation Frequency Deviation vs. Power Supply Volt- 6.8 Oscillation Frequency Deviation vs. Temperature...
  • Page 51 Write to clock and condition will be completed within 0.5 seconds. (The calendar counters RS5C372A/B force access to the CPU to terminate within 0.5 to 1.0 seconds after start condition has occurred in case the CPU is failed during access.)
  • Page 52 Read from clock and condition will be completed within 0.5 seconds. (The calendar counters RS5C372A/B force access to the CPU to terminate within 0.5 to 1.0 seconds after start condition has occurred in case the CPU is failed during access.) Stop condition 7.4 Second Digit Adjustment by ±30 seconds...
  • Page 53 RS5C372A/B 7.5-2 Alarm Interrupt Operation *1) Before setting alarm time, disable alarm function AALE or BALE=0 tentatively by setting AALE or BALE to 0 in case the set time agrees with the current time. Set alarm *2) After all alarm settings have been completed, (hour or minute, day-of-the-week) enable alarm function.
  • Page 54 ■Ricoh awarded ISO 14001 certification. ■Ricoh presented with the Japan Management Quality Award for 1999. The Ricoh Group was awarded ISO 14001 certification, which is an international standard for Ricoh continually strives to promote customer satisfaction, and shares the achievements environmental management systems, at both its domestic and overseas production facilities.

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