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High precision I
OUTLINE
The R2025S/D is a real-time clock module, built in CMOS real-time clock IC and crystal oscillator, connected to
the CPU by two signal lines, SCL and SDA, and configured to perform serial transmission of time and calendar
data to the CPU. The oscillation frequency is adjusted to high precision (0±5ppm: 15sec. per month at 25°C) The
periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5
seconds to 1 month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation
circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and
the time keeping current is small (TYP. 0.48μA at 3V). The oscillation halt sensing circuit can be used to judge the
validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to record a
drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32-kHz clock output
function (CMOS output) is intended to output sub-clock pulses for the external microcomputer. The oscillation
adjustment circuit is intended to adjust time by correcting deviations in the oscillation frequency of the crystal
oscillator.
FEATURES
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Built in 32.768kHz crystal unit, The oscillation frequency is adjusted to high precision (0±5ppm: at 25°C)
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Time keeping voltage 1.15V to 5.5V
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Super low power consumption 0.48μA TYP (1.2μA MAX) at VDD=3V
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I2C-Bus interface (Maximum serial clock frequency: 400KHz at VDD≥1.7V)
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Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,
and weeks) (in BCD format)
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Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to
the CPU and provided with an interrupt flag and an interrupt halt
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2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute
alarm settings)
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32768Hz Clock CMOS push-pull output with control pin
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With Power-on flag to prove that the power supply starts from 0V
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With Oscillation halt sensing Flag to judge the validity of internal data
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Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
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Automatic identification of leap years up to the year 2099
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Selectable 12-hour and 24-hour mode settings
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Oscillation adjustment circuit for correcting temperature frequency deviation or offset deviation
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CMOS process
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Two types of package, SOP14(10.1x7.4x3.1) or SON22(6.1x5.0x1.3)
2
C-Bus Real-Time Clock Module
R2025S/D
NO.EA-135-100825
1
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Summary of Contents for Ricoh R2025S/D
- Page 1 NO.EA-135-100825 OUTLINE The R2025S/D is a real-time clock module, built in CMOS real-time clock IC and crystal oscillator, connected to the CPU by two signal lines, SCL and SDA, and configured to perform serial transmission of time and calendar data to the CPU. The oscillation frequency is adjusted to high precision (0±5ppm: 15sec. per month at 25°C) The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5...
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Page 2: Pin Configuration
R2025S/D PIN CONFIGURATION R2025S (SOP14) R2025D (SON22) CLKC N.C. N.C. N.C. N.C. N.C. N.C. N.C. 32KOUT /INTRB 32KOUT N.C. N.C. N.C. N.C. /INTRA /INTRB N.C. N.C. N.C. /INTRA CLKC N.C. N.C. TOP VIEW TOP VIEW BLOCK DIAGRAM ALARM_W REGISTER 32KOUT... -
Page 3: Pin Description
R2025S/D PIN DESCRIPTION Symbol Item Description Serial The SCL pin is used to input clock pulses synchronizing the input and Clock Line output of data to and from the SDA pin. Allows a maximum input voltage of 5.5 volts regardless of supply voltage. -
Page 4: Absolute Maximum Ratings
R2025S/D ABSOLUTE MAXIMUM RATINGS (VSS=0V) Symbol Item Pin Name and Condition Description Unit Supply Voltage -0.3 to +6.5 Input Voltage 1 SCL, SDA, CLKC -0.3 to +6.5 Input Voltage 2 -0.3 to VDD+0.3 Output Voltage 1 SDA, /INTRA, /INTRB -0.3 to +6.5... -
Page 5: Dc Electrical Characteristics
R2025S/D DC ELECTRICAL CHARACTERISTICS Unless otherwise specified: VSS=0V,VDD=3V,Topt=-40 to +85°C Symbol Item Pin Name Condition Min. Typ. Max. Unit “H” Input Voltage SCL,SDA, VDD=1.7 to 5.5V 0.8x CLKC “L” Input Voltage -0.3 0.2x “H” Output 32KOUT VOH=VDD-0.5V -0.5 Current IOL1 “L”... -
Page 6: Ac Electrical Characteristics
R2025S/D AC ELECTRICAL CHARACTERISTICS Unless otherwise specified: VSS=0V,Topt=-40 TO +85°C Input / Output condition: VIH=0.8xVDD,VIL=0.2xVDD,VOH=0.8xVDD,VOL=0.2xVDD,CL=50pF Symbol Item Condi- Unit VDD≥1.7V tion Min. Typ. Max. SCL Clock Frequency μs SCL Clock ”L” Time μs SCL Clock ”H” Time HIGH μs Start Condition Hold Time HD;STA... -
Page 7: Package Dimensions
R2025S/D PACKAGE DIMENSIONS • R2025S (SOP14) 10.1±0.2 0°-10° +0.1 0.15 -0.05 1.24typ. +0.1 0.35 1.27±0.1 -0.05 • R2025D (SON22) ± 0.2 0.65 A’ ± 0.1 ± 0.1 A’ 0.55typ. ± 0.1 0.125 +0.1/-0.05... -
Page 8: General Description
Clock and Calendar Function The R2025S/D reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. - Page 9 • 32kHz Clock Output The R2025S/D incorporates a 32-kHz clock output circuit configured to generate clock pulses with the oscillation frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin (CMOS push-pull output). The 32-kHz clock output is enabled and disabled when the CLKC pin is held high, and low or open, respectively. The 32-kHz clock output can be disabled by certain register settings but cannot be disabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the CPU.
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Page 10: Address Mapping
R2025S/D Address Mapping Address Register Name D a t a A3A2A1A0 0 0 0 0 Second Counter 0 0 0 1 Minute Counter 0 0 1 0 Hour Counter P⋅/A 0 0 1 1 Day-of-week Counter 0 1 0 0... -
Page 11: Register Settings
R2025S/D Register Settings • Control Register 1 (ADDRESS Eh) WALE DALE /CLEN2 TEST (For Writing) /12⋅24 WALE DALE /CLEN2 TEST (For Reading) /12⋅24 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. - Page 12 R2025S/D (5) CT2,CT1, and CT0 Periodic Interrupt Selection Bits Description Wave form Interrupt Cycle and Falling Timing mode OFF(H) (Default) Fixed at “L” Pulse Mode 2Hz(Duty50%) Pulse Mode 1Hz(Duty50%) Level Mode Once per 1 second (Synchronized with second counter increment)
- Page 13 R2025S/D *1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or 60sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
- Page 14 R2025S/D (5) /CLEN1 32-kHz Clock Output Bit 1 /CLEN1 Description Enabling the 32-kHz clock output (Default) Disabling the 32-kHz clock output Setting the /CLEN1 bit or the /CLEN2 bit (D4 in the control register 1) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
- Page 15 R2025S/D • Time Counter (Address 0-2h) Second Counter (Address 0h) (For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) Minute Counter (Address 1h) (For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *)
- Page 16 R2025S/D • Calendar Counter (Address 4-6h) Day-of-month Counter (Address 4h) (For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) Month Counter + Century Bit (Address 5h) MO10 (For Writing) /19⋅20 MO10 (For Reading) /19⋅20 Indefinite Indefinite...
- Page 17 R2025S/D the Second Counter is incremented once per 32768 32.768-kHz clock pulses generated by the crystal oscillator. Writing to the F6 to F0 bits activates the oscillation adjustment circuit. * The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the Oscillation Adjustment Register.
- Page 18 R2025S/D • Alarm_W Registers (Address 8-Ah) Alarm_W Minute Register (Address 8h) WM40 WM20 WM10 (For Writing) WM40 WM20 WM10 (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) Alarm_W Hour Register (Address 9h) WH20 WH10 (For Writing) WP⋅/A...
- Page 19 R2025S/D Example of Alarm Time Setting Alarm Day-of-week 12-hour mode 24-hour mode Preset alarm time Tue. Wed Fri. Sat. 00:00 a.m. on all days 01:30 a.m. on all days 11:59 a.m. on all days 00:00 p.m. on Mon. to Fri.
- Page 20 R2025S/D Interfacing with the CPU The R2025S/D employs the I C-Bus system to be connected to the CPU via 2-wires. Connection and system of C-Bus are described in the following sections. Connection of I C-Bus 2-wires, SCL and SDA pins that are connected to I C-Bus are used for transmit clock pulses and data respectively.
- Page 21 R2025S/D duration of SDA and SCL pins are the half of bus operation duration. “× 2” in the numerator of the same member is because there are two pins of SDA and SCL. The third member, (charging/discharging times per unit time) means number of transition from “H”...
- Page 22 R2025S/D Start Condition Stop Condition tHD;STA tSU;STO (2) Data transmission and its acknowledge After Start condition is entered, data is transmitted by 1byte (8bits). Any bytes of data may be serially transmitted. The receiving side will send an acknowledge signal to the transmission side each time 8bit data is transmitted.
- Page 23 7bit address is sequentially transmitted from the MSB and 2 and after bytes are read, when 8bit is “H” and when write “L”. The Slave Address of the R2025S/D is specified at (0110010). At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However, if start condition is generated without generating Stop Condition, Repeated Start Condition is met and transmission / receiving data may be continue by setting the Slave Address again.
- Page 24 C-Bus standard defines a transmission format for the slave allocated for each IC, transmission method of address information in IC is not defined. The R2025S/D transmits data the internal address pointer (4bit) and the Transmission Format Register (4bit) at the 1byte next to one which transmitted a Slave Address and a write command.
- Page 25 R2025S/D Example 1 of Data Read (when data is read from 2h to 4h) R/W=0(Write) Repeated Start Condition R/W=1(Read) 0 0 0 Address Transmission Slave Address Slave Address Pointer ← 2h ← (0110010) ← (0110010) Format Register←0h Data Data Data...
- Page 26 R2025S/D The third method to reading data from the internal register is to start reading immediately after writing to the Slave Address and R/W bit. Since the Internal Address Pointer is set to Fh by default as described in the first method, this method is only effective when reading is started from the Internal Address Fh.
- Page 27 Assuming read was started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to 06:00:00 P.M. At this time second digit is hold so read the read as 05:59:59. Then the R2025S/D confirms (Stop Condition) and carries second digit being hold and the time change to 06:00:00 P.M. Then, when the hour digit is...
- Page 28 That is, R2025S/D loses without correction of time counts deviation. Generally, a clock is corrected to gain 3 to 6ppm at 25°C. R2025S/D is corrected it by setting clock adjustment register. Ricoh suggests to set 7Fh to clock adjustment register (Address 7h) for time setting to gain 3ppm at 25°C, for the equipment used indoors.
- Page 29 1. Using oscillator adjustment function 2. Access to R2025S/D at random, or synchronized with external clock that has no relation to R2025S/D, or synchronized with periodic interrupt in pulse mode. 3. Access to R2025S/D more than 2 times per each second on average.
- Page 30 R2025S/D error as follows: (1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh. (2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60 seconds) like next page figure.
- Page 31 R2025S/D Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring • PON, /XST, and VDET The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses.
- Page 32 R2025S/D Threshold voltage (2.1V or 1.3V) 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag (/XST) VDD supply voltage monitor flag (VDET) VDET←0 VDET←0 VDET←0 Internal initialization Internal initialization /XST←1 /XST←1 /XST←1 period (1 to 2 sec.) period (1 to 2 sec.) PON←0...
- Page 33 R2025S/D • Voltage Monitoring Circuit The VDD supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.3v for the VDSL bit setting of 0 (the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as illustrated in the timing chart below.
- Page 34 R2025S/D Alarm and Periodic Interrupt The R2025S/D incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals, respectively, for output from the /INTRA or /INTRB pins as described below.
- Page 35 R2025S/D this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0.
- Page 36 R2025S/D *1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below. CTFG Bit /INTRA Pin Approx. 92 μ s (Increment of second counter) Rewriting of the second counter In the pulse mode, the increment of the second counter is delayed by approximately 92 μ...
- Page 37 (D4 at Address (CMOS push-pull output) 0(Default) 32kHz clock output 0(Default) For the R2025S/D, the 32KOUT pin output is synchronized with CLKC pin input as illustrated in the timing chart below. CLKC pin (/CLEN1 or /CLEN2= 0) 32KOUT pin Max.76.3μs...
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Page 38: Typical Applications
Sample circuit configuration 1 *1) Install bypass capacitors for high-frequency and low-frequency applications in parallel in close System power supply vicinity to the R2025S/D. Sample circuit configuration 2 System power supply *1) When using an OR diode as a power supply... - Page 39 Connection of 32KOUT Pin As the 32KOUT pin is CMOS output, the power supply voltage of the R2025S/D and any devices to be connected to the 32KOUT should be same. When the devices is powered down, the 32KOUT output should be disabled.
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Page 40: Typical Characteristics
R2025S/D Typical Characteristics Test Circuit V DD Topt : 25 ° C Output : Open SCL, SDA pin : VDD or VSS Frequency 32KOUT Counter V SS Timekeeping current vs. Supply Voltage Timekeeping current vs. Supply Voltage (with no 32-kHz clock output) (with 32-kHz clock output) (Output=Open,Topt=25 °... - Page 41 R2025S/D Oscillation Frequency Deviation vs. Supply Voltage Oscillation Frequency Deviation vs. (Topt=25 ° C) Operating Temperature (VDD=3v) -100 -120 -60 -40 -20 80 100 Power Supply VDD (v) Operating Temperature Topt(Celsius) VOL vs. IOL(/INTRA, /INTRB pin) CLKC pin Input Current vs. Power Supply (Topt=25 °...
- Page 42 *4) Take care so that process from Start Condition to Stop Condition will be Calendar Counter complete within 0.5sec. (Detailed in "P.27 Data Transmission under Special Condition". Write to Clock Adjustment The R2025S/D may also be initialized not at power-on but in the process Register of writing time and calendar data. Stop Condition...
- Page 43 R2025S/D • Reading Time and Calendar Data (1) Ordinary Process of Reading Time and Calendar Data *1) When reading to clock and calendar counters, do not insert Stop Condition until all times from second to year have been written to prevent Start Condition error in writing time.
- Page 44 R2025S/D (3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading.
- Page 45 R2025S/D • Interrupt Process (1) Periodic Interrupt *1) This step is intended to select the level mode as a Set Periodic Interrupt waveform mode for the periodic interrupt function. Cycle Selection Bits *2) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.
- Page 46 R2025S/D Land Pattern (reference) • R2025S (SOP14) 1.27 P 1.27x6=7.62 unit:mm 8.32 Package top view 1. Pad layout and size can modify by customers material, equipment, and method. Please adjust pad layout according to your conditions. 2. In the mount area which descried as , is close to the inside oscillator circuit.
- Page 47 R2025S/D • R2025D (SON22) 0.25 0.75 0.25 P 0.5x10=5.0 unit : mm 5.25 Package top view Package bottom view 1. Pad layout and size can modify by customers material, equipment, and method. Please adjust pad layout according to your conditions.
- Page 48 ■Ricoh awarded ISO 14001 certification. ■Ricoh presented with the Japan Management Quality Award for 1999. The Ricoh Group was awarded ISO 14001 certification, which is an international standard for Ricoh continually strives to promote customer satisfaction, and shares the achievements environmental management systems, at both its domestic and overseas production facilities.
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