Roland CR-78 Service Notes

JUNE
20,
1979 CR-78
CR-78
SERVICE NOTES
Panel
no. 255
(072-235)
Pots
.
LYE
6
B 001
- 10 KB
(
029
-
410
)
Pot.
EVHCOAP25B14
(026-021)
Switch
SRMIOIC
(
001
-
242
)
Knob no. 44
(016-044) _
Knob
No
.
48
(
016
-
048
)
Pot
.
LYE6B001-50KB
(029-411)
Pot
.
BVHCOAP25B15
(026-024)
Knob
No. 45
(016-043)
LED SIP-1 31B
—
I
(red)
(019-013)
Swith
SUP55
(001-241)
I^ob No. 80
(
016
-
080
)
'Switch
SDG5P
(001-215)
lOOV
(001-216)
117V
(001-217)
220/240V
Knob No. 81
_
(016-081)
Switch
SRA202B
(001-244)
LED SLP-151B red
(019-013)
Switch
—
SRM1025
(001-245)
P Switch
SLR-
5 25
(001-245)
Switch
SLR-825
(
o
/I
/C ^
\
WW_L
—
J
Knob No. 67
(016-067)
_
Switch
SLR-522
(001-231)
Switch
KCA10057
(001-273)
Switch
KCA10057
(001-273)
Switch
SLR-522
(001-251)
Cabinet No. 115
(081-113)
Base (foot) No. 20
(
111 -
020
)
Switch
SUEA2
(001-259)
Switch
SUEB2 (001-240) Buttons
8'16'COMBI TRIGGER OUT
START/STOP
VARIATION
I
—
uu
HIGH IMP
CM]
Switch HSW0572-01-050
(001-206)
Jacks SG7622 #8 (009-012)
(016-008)
G-ray
(016-085)
White
(016-086)
Red
(016-087)
Green
(016-088)
Yellow
(016-089) Blue
Printed
in
Japan
Jul.
'82 E-2
LOGIC
SYMBOL
F4013
CONNECTION DIAGRAM
DIP
(TOP VIEW)
'L
7
'^''dd
Q,
Qj
CP,
-'ll
Cot Ci>2
^1
C02
,o
eC
3di 02
<
''SS
Sp2
NOTE;
The
Flatpak version has the
same
pinouts (Connection Diagram)
as
the
Dual In-line Package.
F4013 TRUTH TABLES
SYNCHRONOUS
INPUTS
OUTPUTS
CP D
Qn+1 Qn-M
-T
L
S
H
L H
H
L
Conditions:
Sp
=
Cq
=
LOW
ASYNCHRONOUS
INPUTS
OUTPUTS
Sd
Cq
Q
Cl
L H
H
L
H H
L
H
H L
L L
L
» LOW
Level
H "HIGH
Level
S
"
Positive-Going Transition
X " Don't Care
Qfi
+1 " State After Clock Positive Transition
F4001 QUAD
2-INPUT
NOR GATE
F4001
LOGIC
AND
CONNECTION DIAGRAM
DIP (TOP VIEW)
'^DD
fJ
1
fh]
R
[J] [L] rn Y]
LfeJ
L<^
r
LE
[ij
UJ
bJ hJ
lij LzJ
^ss
SN74LS174.
SN74LS175.
F40175
SN54174, SN54LS174, SN54S174
. . .
J
OR
W
PACKAGE
SN74174, SN74LS174, SN74S174
.
. .
J
OR N PACKAGE
(TOP VIEW)
Vcc 60 60 SO SO 40 40 CLOCK
mjij
m
n m
m
m
mioi
1
1
|B
]
c
L. D Q -
-C
>CK
CLEAR
i
B
c
L-,'
AR
CK< >
7±z
CLEAR
-<
>CK
f-
D 0
C
]
i
wm
iJ 3
NT
01
line
CLEAR 10
1D 20
20
30 30
GNO
DECODERS/DEMULTIPIEXERS
SN54LS138, SN54S138
. . .
J
OR
W
PACKAGE
SN74LS138, SN74S138
. . .
J
OR N PACKAGE
(TOP VIEW)
V2 Y3 Y4 Y5
Y6^
LS138,
S138
DATA
OUTPUTS
LS138, S138
FUNCTION TA8LE
INPUTS
OUTPUTS
ENABLE SELECT
G1 G2*
C
B
A YO Y1 <
to
Y3 Y4 Y5
Y6 Y7
X
H X X X H H H H H H H H
L
X X X
X H H H H H H H H
H L L L L L
H H H H H H H
H L L L H
H
L H
H H H H H
H L L H L H H L H
H H H H
H
L L
H H H H H L
H H H H
H
L
H
L
L H H H H L
H
H
H
H L
H
L
H H H H H H L H H
H L
H H
L
H H H H H H L H
H L H H H
H H
H
H H H H
L
•G2
=
G2A
t
G2B
H
= high level,
L " low
level,
X - irrelevant
SN54175, SN54LS175, SN54S175
. . .
J
OR
W
PACKAGE
SN74175, SN74LS175, SN74S175
. . .
J
OR N PACKAGE
(TOP VIEW)
NOTE:
In
using F40175
,
refer to note
on
page
8.
QUADRUPLE
D-TYPE FLIP-FLOPS
FUNCTION TABLE
(EACH FLIP-FLOP)
1
INPUTS
1 1
OUTPUTS
1
i
CLEAR CLOCK D Q Qt
L
X X
L H
H
t
H
H
L
H
t
L L H
H L X
Qo
H
" high level (steady state)
L low level (steady state)
X •
irrelevant
t
•
transition from low to high level
CXq
» the
level of
Q
before the indicated steady-state
input conditions
were
established.
^ "
'175, 'LSI 75,
and
*S
1
75
only
HEX INVERTERS
Vcc &A 6Y 5A 5Y 4A 4Y
f—
1
r—
1 -t— t
f—
4 i— -I r—t r-|-j
1[>J
1[>J
hukuki
ULUTBliJIiJIiJ-lif
1A IV
2A 2V 3A
3Y
GND
SNS404
(J)
SN54H04
(J)
SNB4L04
(J)
SN54LS04 U, W)
SN54S04 U.W)
SN7404
(J, N)
SN74H04
(J, N)
SN74L04
(J,
N)
SN74LS04
(J, N)
SN74S04
(J, N)
QUADRUPLE 2-INPUT
POSITIVE-NANO
GATES
SN54(X) (J)
SN74(X)
(J. N)
SN54HCX)
(J)
SN74HOO
(J,
N)
SN54LQ0
(J)
SN74L00
(J,
N)
SN54LS(X)
(J,
W) SN74LS00
(J,
N)
SNS4S00(J,W) SN74S00(J,N)
Roland