Related Manuals for Sundance Spas SMT377
Summary of Contents for Sundance Spas SMT377
- Page 1 SMT377 User Manual User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999...
- Page 2 Version 0.9 Page 2 of 24 SMT377 User Manual Revision History Date Comments Engineer Version 16/05/02 First release...
- Page 3 ..................16 Via CommPort3..................... 16 Via JTAG....................... 17 Via X-Checker....................... 18 Getting control of the SMT377.................. 19 DAC Control – DAC output................... 20 DAC Control – Load SRG0 and SRG1..............20 Memory Control – Load start address..............21 Memory Control –...
- Page 4 Version 0.9 Page 4 of 24 SMT377 User Manual Output signal - dynamic..................23 Output signal – Static.................... 24...
- Page 5 Version 0.9 Page 5 of 24 SMT377 User Manual Table of figures. Figure 1 - Block diagram..................... 8 Figure 2 - External VBatt connector (J16)..............10 Figure 3 - SDB/LVDS hardware selection..............12 Figure 4 - External 2.5 volts - LVDS mode............... 13 Figure 5 - Example of installation on an SMT320.
- Page 6 Version 0.9 Page 6 of 24 SMT377 User Manual Contacting Sundance You can contact Sundance for additional information by sending email to support@sundance.com...
- Page 7 SMT377 User Manual Outline Description The SMT377 (377) is a single width TIM, which provides 8 channels of DAC output using two Burr Brown DAC7634 devices. It is offering the following features: 8 channels of DAC outputs, using 16-bit Burr Brown DAC7634 devices, with a settling time of 10us to 0.003%.
- Page 8 Page 8 of 24 SMT377 User Manual Block Diagram. The following diagram shows interconnections between main blocks of the SMT377. Greyed out blocks represent the main devices fitted on the board. Other blocks are on-board connectors or secondary devices. J1 Top Primary TIM Connector Comm-Port 0 &...
- Page 9 Version 0.9 Page 9 of 24 SMT377 User Manual Architecture description. The module consists of two DAC7634-quad digital to analogue converters (DAC). They are serially connected to a Xilinx Virtex-II FPGA, which is responsible for transferring the output samples to the DACs.
- Page 10 The key are stored in the FPGA by JTAG instruction and retained by a Vbatt voltage, when the device is not powered. The SMT377 have no on-board battery to provide this Vbatt voltage to the FPGA, but has a connector (J16) from where the user can provide an external supply.
- Page 11 (token exchange) that will reverse the state of both ends of the link. One the SMT377, only CommPorts 0, 1, 2, 3 and 4 are available. Following a processor reset, the first three links (0, 1, and 2) initialise as transmitters and the remainder (3, 4, and 5) initialise as receivers.
- Page 12 To have details on the CommPort interface, refer to: http://www.sundance.com/ SDB/LVDS. The SMT377 provides two Sundance Digital Buses (SDBs). These 16-bit data parallel links for synchronous transmission can achieve high-speed data transfer across 40-way flat ribbon cables with ground-interlaced 3.3v signals (Ref. SMT3xx- SDB-CAB).
- Page 13 Version 0.9 Page 13 of 24 SMT377 User Manual FPGA. Position ‘0’ takes the on-board 3.3 Volts to the I/O pads of the FPGA. The following picture shows the location of J4, DR35 and DR36: Figure 4 - External 2.5 volts - LVDS mode.
- Page 14 SMT377 User Manual Installation. The minimum system requirements needed to run an SMT377 on a PC is a carrier board (SMT320, SMT310Q, SMT327, SMT300Q) and a C6x TIM with at least a transmitter CommPort (CommPort 0,1 or 2) at Reset available, to connect the processors to CommPort 3 of the SMT377.
- Page 15 Version 0.9 Page 15 of 24 SMT377 User Manual Figure 6 - Example of installation - CommPort connection.
- Page 16 The FPGA configuration is done by a software routine running (provided by Sundance) on a host (C6x processor) that downloads a bitstream to the Virtex-II via the CPLD using CommPort3 (on the SMT377). Once the FPGA is configured, the LED L1 (top right corner) lights up.
- Page 17 SMT377. Via JTAG. The FPGA configuration can be also done by JTAG. On the SMT377, both CPLD and FPGA are part of the JTAG chain. Make sure that you don’t erase the CPLD.
- Page 18 CPLD. Be careful not to erase the CPLD. Via X-Checker. The FPGA configuration can be also done by an X-Checker cable. On the SMT377, pins from this connector are only connected to the FPGA. The 7-pin header located on the top side of the board has the following pinout:...
- Page 19 SMT377 User Manual Getting control of the SMT377. The SMT377 once configured needs to receive a control word via CommPort 3 to start converting digital data into analogue. The board consists of 8 DAC channels. Each channel is interfaced with one FIFO all implemented in the Virtex-II FPGA.
- Page 20 Stop Pattern generator Reset internal FIFOs Figure 11 - Control register. Bits 31-28 determine the function of the bits 27-0. Here is the detail of all the functions available to control the SMT377. DAC Control – DAC output. 27…21 18…16 15…0...
- Page 21 Version 0.9 Page 21 of 24 SMT377 User Manual Memory Control – Load start address. 27…21 20…0 Not used. Start address Memory Control – Size burst. 27…21 20…0 Not used. Burst size Memory Control – Load data for memory. 27…16 15…0...
- Page 22 Version 0.9 Page 22 of 24 SMT377 User Manual Miscellaneous – Reset internal FIFOs. 27…0 Not used. There is no parameter for this command; it resets FIFOS of each DAC Channel.
- Page 23 Page 23 of 24 SMT377 User Manual DAC Analogue outputs. The SMT377 has 8 analogue outputs. Each of them can be independently non- amplified or amplified by an output op-amp. Output mode: Amplified, non-amplified. 0-Ohm resistors located at the back of the board are used to do a hardware selection between both modes, as shown on the following picture: Figure 12 - Output hardware configuration.
- Page 24 Version 0.9 Page 24 of 24 SMT377 User Manual Output signal – Static. DAC7634s are 16-bit DACs, which give them a good accuracy. They can be used for example for position regulation. A bit of a sample data represents 38 µVolts.
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