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Sundance Spas SMT335E User Manual

Sundance Spas SMT335E User Manual

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SMT335E
SMT375E
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001

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  • Page 1 SMT335E SMT375E User Manual User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001...

  • Page 2: Revision History

    Version 3.0 Page 2 of 53 SMT335E SMT375E User Manual Revision History Date Comments Engineer Version 04/04/01 Copy from SMT335E V1.1 J.V. 12/06/02 JTAG Header for FPGA reprogramming added J.V. Interrupt control register 6 address corrected FPGA firmware version 1.1...

  • Page 3: Table Of Contents

    Reprogramming the firmware and boot code ............11 Interrupts ......................... 12 Interrupt Control Register ..................12 Communication ports..................... 14 Overview ....................... 14 Comm-ports on the SMT335E................15 Comm-port Status and Control Register ............... 16 Global Status Register ..................19 Data rates......................20 SDB .......................... 21 SDB Status Register .....................
  • Page 4 Version 3.0 Page 4 of 53 SMT335E SMT375E User Manual Suspending SDB transmission ................26 Bus exchange ....................... 26 SDB Clock selection....................27 Data formatting...................... 27 Global bus ....................... 28 Writing to the Global Bus..................28 Reading from the Global Bus ................29 Global Bus Operation Register................

  • Page 5: Contacting Sundance

    Version 3.0 Page 5 of 53 SMT335E SMT375E User Manual JP2: Serial port header..................45 - Fan power connector ................46 SDB Pin-Out ......................46 Virtex Pin-Out ......................48 Bibliography......................51 Index ........................52 Contacting Sundance You can contact Sundance for additional information by sending email to...

  • Page 6: Notational Conventions

    Notational Conventions SMT335E Throughout this document the term SMT335E will usually be used to refer to both the SMT335E and the SMT375E. It should be clear from the context when a distinction is being drawn between the two types of module.

  • Page 7: Outline Description

    Version 3.0 Page 7 of 53 SMT335E SMT375E User Manual Outline Description The SMT335E is a C6000-based size 2 TIM offering the following features: SMT335E: TMS320C6201 processor running at 200MHz SMT375E: TMS320C6701 processor running at 166MHz Six 20MB/s communication ports...

  • Page 8: Block Diagram

    S erial P orts Architecture Description The SMT335E TIM consists of a Texas Instruments TMS320C6201 running at 200MHz while the SMT375E has a TMS320C6701 running at 166MHz. Modules are populated with 512KB of synchronous burst SRAM (SBSRAM) and 16MB of synchronous DRAM (SDRAM), giving a total memory capacity of 16.5MB.

  • Page 9: Tms320C6201/6701

    Boot Mode The SMT335E is configured to use the following boot sequence each time it is taken out of reset: 1. The processor copies a bootstrap program from the first 32KB of the flash memory into internal program RAM starting at address 0.

  • Page 10: Emif Control Registers

    Version 3.0 Page 10 of 53 SMT335E SMT375E User Manual EMIF Control Registers The C6000 contains several registers that control the external memory interface (EMIF). There is one global control register and a separate register for each of the memory spaces CE0 to CE3. A full description of these registers can be found in the C600001 Peripherals Reference Guide[1].

  • Page 11: Reprogramming The Firmware And Boot Code

    Version 3.0 Page 11 of 53 SMT335E SMT375E User Manual Reprogramming the firmware and boot code The Reprogramming\flash directory of the distribution disk contains a utility that will run under code composer and program the flash ROM. The utility is called pflashx_y_z.out, where x_y_z is the FPGA version number.

  • Page 12: Interrupts

    Version 3.0 Page 12 of 53 SMT335E SMT375E User Manual Interrupts The generation of a CPU interrupt by a comm-port, an SDB, or the Global Bus starts when the FPGA asserts an interrupt condition. For example, this may be the result of an input FIFO becoming not empty or an output FIFO not full.
  • Page 13 Version 3.0 Page 13 of 53 SMT335E SMT375E User Manual IFBM=0 not empty Comm-port Input FIFO CPx IE(bit 0) Interrupt Enable IFBM=1 8 words available Comm-port Output FIFO OFBM=0 not full CPx IE (bit 1) Interrupt Enable OFBM=1 8 spaces available...

  • Page 14: Communication Ports

    SMT335E SMT375E User Manual Communication ports Overview The SMT335E provides six 8-bit, data-parallel, inter-processor links that follow Texas Instruments’ TMS320C4x Communication Port standard. Additional information on the standard is available in the TMS320C4x User’s Guide chapter 12: Communication ports and the Texas Instrument Module Specification.

  • Page 15: Comm-Ports On The Smt335E

    Page 15 of 53 SMT335E SMT375E User Manual Comm-ports on the SMT335E An SMT335E TIM has access to six FIFO-buffered comm-ports, fully compliant with the Texas Instruments’ standard [3]. Each comm-port is associated with two 15x32-bit unidirectional FIFOs; one for input and one for output.

  • Page 16: Comm-Port Status And Control Register

    Version 3.0 Page 16 of 53 SMT335E SMT375E User Manual Comm-port Status and Control Register CP0_STAT 0x03040000 CP3_STAT 0x031C0000 CP1_STAT 0x030C0000 CP4_STAT 0x03240000 CP2_STAT 0x03140000 CP5_STAT 0x032C0000 31–28 23–20 19–16 15–12 11-8 R,0000 R,1111 ICPRDY OCPRDY CLRCP IFBM OFBM CLRIF...
  • Page 17 Version 3.0 Page 17 of 53 SMT335E SMT375E User Manual There is a control and status register for each of the six comm-ports. There is also one read-only Global Comm-port Status Register that gathers status from all comm- ports in one place.
  • Page 18 Version 3.0 Page 18 of 53 SMT335E SMT375E User Manual Interrupts: The comm-port control logic can assert an interrupt condition as the result of data being transferred. The condition indicates that either one word or a block of 8 words has been moved. The bits IFBM and OFBM in the comm-port control and status register select which condition will assert the interrupt line.

  • Page 19: Global Status Register

    Version 3.0 Page 19 of 53 SMT335E SMT375E User Manual Global Status Register STAT 0x033C0000 31–30 29–28 27–26 25–24 23–22 21–20 19–18 17–16 SDBA SDBB STAT_INT STAT_INT STAT_INT STAT_INT STAT_INT STAT_INT STAT_INT STAT_INT R,10 R,10 R,10 R,10 R,10 R,10 R,10 R,10 15–14...

  • Page 20: Data Rates

    Version 3.0 Page 20 of 53 SMT335E SMT375E User Manual Data rates When using the communication links of a C6000 you must remember that the links share a single bus, so the performance you get will depend on the way you sequence bus accesses.

  • Page 21: Sdb

    Page 21 of 53 SMT335E SMT375E User Manual The SMT335E provides four Sundance Digital Buses (SDBs). These 16-bit data parallel links for synchronous transmission can achieve high-speed data transfer across 40-way flat ribbon cables with ground-interlaced 3.3v signals (Ref. SMT3xx- SDB-CAB).

  • Page 22: Sdb Status Register

    Version 3.0 Page 22 of 53 SMT335E SMT375E User Manual SDB Status Register SDBA_STAT 0x03480000 SDBB_STAT 0x03580000 31–30 23–16 IFLAG OFLAG R,00000000 15–8 TRANS SDBCLK CLRIF CLROF R,11111111 RW,0 RW,0 RW,0 RW,0 Field Description (flags are active when 1) 0 Reading...

  • Page 23: Output Flag Register

    Version 3.0 Page 23 of 53 SMT335E SMT375E User Manual Output Flag Register SDBA_OUTPUTFLAG 0x034C0000 SDBB_OUTPUTFLAG 0x035C0000 31–24 23–16 15–8 7–0 OTRIGGER R,00000000 RW,10000000 R,00000000 R,10000000 Input Flag Register SDBA_INPUTFLAG 0x03440000 SDBB_INPUTFLAG 0x03540000 31–24 23–16 15–8 7–0 ITRIGGER R,00000000 R,10000000...

  • Page 24: Sdb Interrupts

    SMT335E SMT375E User Manual SDB Interrupts The SMT335E has been designed to allow transfers to be controlled by interrupt conditions. The main constraint in the design was to make sure that only one interrupt condition could be generated for each frame of data. This cannot be done directly by mapping the FIFO flags to interrupt lines because the flags can generate many edges during a transfer.

  • Page 25: Dma

    Version 3.0 Page 25 of 53 SMT335E SMT375E User Manual SDB transfers can be performed using DMA without any processor interaction. The DMA should be set to transfer frames of up to 255 words, with read synchronisation on the SDB’s interrupt condition. The FIFO must be addressed using consecutive word addresses to allow for correct synchronisation;...

  • Page 26: Sdb Initialisation

    TRANS once the clocks have started running will have any effect. When two SMT335E SDBs are connected it does not matter which end is set to be a transmitter. When connecting an SMT335E to an older, input-only SDB, the SMT335E SDB must be made a transmitter.

  • Page 27: Sdb Clock Selection

    Version 3.0 Page 27 of 53 SMT335E SMT375E User Manual SDB Clock selection At any time you can change the speed of an SDB clock by altering SDBCLK. Module SDBCLK Clock Speed 50MHz SMT335E 100MHz 41MHz SMT375E 83MHz Data formatting 32-bit words are sent in two 16-bit packets with the least significant bits being sent first.

  • Page 28: Global Bus

    SMT335E SMT375E User Manual Global bus The SMT335E provides a global bus that is compatible with the TIM standard. A dual port RAM (DPR) is used as intermediate storage for transfers of data frames between the C6000 and an external device on the global bus; each frame can have up to 256 32-bit words.

  • Page 29: Reading From The Global Bus

    Version 3.0 Page 29 of 53 SMT335E SMT375E User Manual Reading from the Global Bus First specify the trigger value in the Operation Register as described above. At the same time that you set the trigger you must also set the OPERATION bit to 0 indicating that data is to go to the C6000 from the global bus.

  • Page 30: Global Bus Operation Register

    Version 3.0 Page 30 of 53 SMT335E SMT375E User Manual Global Bus Operation Register GLOBAL_BUS_LENGTH 0x03900000 31–9 7–0 OPERATION TRIGGER RW,0 RW,00000000 Field Description OPERATION Read from the Global Bus Write to the Global Bus TRIGGER One less than the number of words to move...

  • Page 31: Pci Access

    Version 3.0 Page 31 of 53 SMT335E SMT375E User Manual PCI access You must make sure you know how to configure your carrier board for PCI transfers; the following example is for the SMT320. To configure the carrier board for PCI transfers you must write two words to the...
  • Page 32 Version 3.0 Page 32 of 53 SMT335E SMT375E User Manual Example of writing a number ( ) frames, each of 1024 bytes size int *ptr_gbctrl = (int *) 0x03800000; int *ptr_gbstart_addr = (int *) 0x03880000; int *ptr_gblenth = (int *) 0x03900000;...
  • Page 33 Version 3.0 Page 33 of 53 SMT335E SMT375E User Manual Example of reading a number ( ) frames, each of 1024 bytes size int *ptr_gbctrl =(int*) 0x03800000; int *ptr_gbstart_addr =(int*) 0x03880000; int *ptr_gblenth =(int*) 0x03900000; // Bit 9 sets read or write int *ptr_gbdpram =(int*) 0x03A00000;...

  • Page 34: Programmable Wait States

    SMT335E SMT375E User Manual Programmable Wait States The SMT335E has its own internal software-configurable wait-state generator that is used in conjunction with the external ready line, RDY. You control the generator by configuring two fields in the Global Bus Control Register: WTCNT specifies the number of software wait states to generate and SWW selects one of four options.

  • Page 35: Clock Speed

    Version 3.0 Page 35 of 53 SMT335E SMT375E User Manual Clock Speed You must consider EMIF device speeds when choosing the appropriate C6000 clock speed. Under most circumstances, the C6201 would be set to 200MHz and have an SBSRAM speed equal to the core speed; the C6701 would be set to 166MHz. See the description of jumper JP1 on page 45.

  • Page 36: Config & Nmi

    This signal, on a standard C4x based TIM, is connected to the processor’s IIOF3 pin. On the SMT335E/375, the CONFIG signal is asserted after power on, and can be released by writing the value (1<<7) to the config register. Conversely, CONFIG may be re-asserted by writing 0 to this bit.

  • Page 37: Timer

    Version 3.0 Page 37 of 53 SMT335E SMT375E User Manual Timer The TIM TCLK0 and TCLK1 signals can be routed to the DSP’s TOUT/TINP pins. The signal direction must be specified, together with the routing information in the timer control register.

  • Page 38: Code Composer

    SMT320V4, SMT327, SMT328 and TI’s XDS-510. Application Development You can develop code for SMT335E/375 modules in several ways. The simplest is to use the Sundance SMT6000 Server Loader and its associated libraries. The Server Loader is an application that runs on a host PC under either Windows 98 or NT and allows you to run COFF-format applications.

  • Page 39: Operating Conditions

    The module must be fixed to a TIM40-compliant carrier board. The SMT335E TIM is in a range of modules that must be supplied with a 3.3v power source. In addition to the 5v supply specified in the TIM specification, these new generation modules require an additional 3.3v supply to be presented on the two...

  • Page 40: Power Consumption

    Version 3.0 Page 40 of 53 SMT335E SMT375E User Manual Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and I/O activity. The figures will be added to the document.

  • Page 41: Serial Ports

    Version 3.0 Page 41 of 53 SMT335E SMT375E User Manual Serial Ports The C6000 contains two multichannel buffered serial ports (McBSP). The signals involved are connected to a 0.1” pitch DIL pin header (JP2). For a full description of signal activity and the serial protocols available, please refer to Chapter 11 of [1].

  • Page 42: C6201 Memory Map

    Version 3.0 Page 42 of 53 SMT335E SMT375E User Manual C6201 Memory Map Starting Address RESOURCE Refer to 00000000 Internal Program RAM 00010000 Reserved External Memory Space CE0 00400000 – 0047FFFF SBSRAM 512KB SBSRAM External Memory Space CE1 01400000 – 015FFFFF...

  • Page 43: Virtex Memory Map

    Version 3.0 Page 43 of 53 SMT335E SMT375E User Manual Virtex Memory Map Resource Comm port 0 FIFO Comm port 0 Status/Control Comm port 1 Comm port 2 Comm port 3 Comm port 4 Comm port 5 Global Status SDB A FIFO...
  • Page 44 Version 3.0 Page 44 of 53 SMT335E SMT375E User Manual The memory mapping is available in SMT335E.h as follows: #define SMT335ECP0 (volatile unsigned int *)0x03000000 #define SMT335ECP1 (volatile unsigned int *)0x03080000 #define SMT335ECP2 (volatile unsigned int *)0x03100000 #define SMT335ECP3 (volatile unsigned int *)0x03180000...

  • Page 45: Jumpers

    Version 3.0 Page 45 of 53 SMT335E SMT375E User Manual Jumpers JP1: Clock speed select C6000 CLK (MHz) S0, S1 and S2 refer to the following link positions on JP1. S2 S1 S0 JP2: Serial port header Refer to the TMS320C6201 Peripheral Reference Guide [1] for a description of the signals and their usage.

  • Page 46: Jp3 - Fan Power Connector

    Version 3.0 Page 46 of 53 SMT335E SMT375E User Manual Fan power connector This connector supplies 5V DC power for the Virtex cooling fan. External 5V supply This connector (standard disk drive connector) is used to supply additional 5V power to the module.
  • Page 47 Version 3.0 Page 47 of 53 SMT335E SMT375E User Manual SDB Pin-Out Signal Signal...

  • Page 48: Virtex Pin-Out

    Version 3.0 Page 48 of 53 SMT335E SMT375E User Manual Virtex Pin-Out SDBB_CLK_BG SDBD_DATA<8> SDBB_DATA<0> C5P<10> SDBD_DATA<7> NRESET C5P<0> SDBD_DATA<10> CLKEXT C5P<1> SDBD_DATA<9> C3P<6> C5P<2> SP2_DR SDBD_DATA<12> C4P<4> C5P<8> SP2_CLKR SDBD_DATA<11> C3P<1> C5P<9> SP2_CLKX C5P<7> C5P<3> SP2_CLKS SDBD_DIR SDBB_CLK_IO C5P<4>...
  • Page 49 Version 3.0 Page 49 of 53 SMT335E SMT375E User Manual NBE<3> ED<24> EA<13> ED<3> ED<25> ED<23> EA<12> ED<2> ED<22> LED<4> ED<1> ED<21> INT5 ED<0> C3P<11> ED<20> NTIMNMI ED<19> C0P<0> ED<18> EA<10> ARDY ED<17> EA<9> LED<5> NAWE ED<16> EA<8> LED<3> NAOE ED<15>...
  • Page 50 Version 3.0 Page 50 of 53 SMT335E SMT375E User Manual C0P<3> AJ12 C2P<8> AL28 HPINDS2 AK23 SDBC_CLK_IO C0P<4> AN11 C2P<3> AL30 HPID<3> AL24 SDBC_DATA<0> C0P<9> AK12 C2P<2> AN28 AN26 SDBC_DIR IIOF1 C0P<10> AK13 SDBA_WEN AJ18 IIOF0 C0P<11> AL13 SDBA_U1 AN19...

  • Page 51: Bibliography

    Version 3.0 Page 51 of 53 SMT335E SMT375E User Manual Bibliography 1. TMS320C6201/C6701 Peripherals Reference Guide (literature number SPRU190) describes common peripherals available on the TMS320C6201/C6701 digital signal processors. This book includes information on the internal data and program memories, the external memory interface (EMIF), the host port, multichannel-buffered serial ports, direct memory access (DMA), clocking and phase-locked loop (PLL), and the power-down modes.

  • Page 52: Index

    Version 3.0 Page 52 of 53 SMT335E SMT375E User Manual Index Application Development....38 field values after reset ..... 6 Flash..........10 server-loader ........ 38 access .......... 42 Architecture Description ....8 Bibliography........51 protection algorithm ...... 10 Block Diagram........8 FPGA ..........
  • Page 53 Version 3.0 Page 53 of 53 SMT335E SMT375E User Manual waning about use ......36 using DMA........25 Notational Conventions....6 using DMA Global Indexes ... 25 Operating Conditions ....39 using old-style SDBs ....26 Output Flag Register ..... 23 Power versions ........

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