Related Manuals for NuDAQ DAQ-2204
Summary of Contents for NuDAQ DAQ-2204
- Page 1 NuDAQ ® DAQ-2204/2205/2206 PXI-2204/2205/2206 64-CH, High Performance Multi-function Data Acquisition Cards User's Guide Recycle Paper...
- Page 2 Trademarks ® ® ® ® NuDAQ , NuIPC , NuDAM , NuPRO are registered trademarks of ADLINK Technology Inc. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered...
- Page 3 Customer Satisfaction is the most important priority for ADLINK Tech Inc. If you need any help or service, please contact us. ADLINK Technology Inc. Web Site http://www.adlinktech.com Sales & Service Service@adlinktech.com NuDAQ + USBDAQ nudaq@adlinktech.com Technical Automation automation@adlinktech.com Support NuIPC nuipc@adlinktech.com...
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Page 4: Table Of Contents
Table of Contents Tables..................iv Figures ..................v How to Use This Guide ............vii Chapter 1 Introduction ............1 1.1 Features ................1 1.2 Applications ..............3 1.3 Specifications ..............3 1.4 Software Support ............. 12 1.4.1 Programming Library ..............12 ® 1.4.2 D2K-LVIEW: LabVIEW Driver.......... - Page 5 Chapter 4 Operation Theory ..........24 4.1 A/D Conversion............... 24 4.1.1 DAQ/PXI-2204 AI Data Format ..........25 4.1.1.1 Synchronous Digital Inputs (for DAQ/PXI-2204 only) ..... 25 4.1.2 DAQ/PXI-2205/2206 AI Data Format ........27 4.1.3 Software conversion with polling data transfer acquisition mode (Software Polling) ................
- Page 6 4.5 Trigger Sources ............... 54 4.5.1 Software -Trigger................54 4.5.2 External Analog Trigger .............. 54 4.5.2.1 Below-Low analog trigger condition ........55 4.5.2.2 Above-High analog trigger condition ........56 4.5.2.3 Inside-Region analog trigger condition ........56 4.5.2.4 High-Hysteresis analog trigger condition......... 57 4.5.2.5 Low-Hysteresis analog trigger condition........
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Page 7: Tables
Tables Table 1: Programmable input range........4 Table 2: -3dB small signal bandwidth ........5 Table 3: System Noise ............6 Table 4: Input impedance ............ 6 Table 5: CMRR (DC to 60Hz) ..........6 Table 6: Settling time to full-scale step......... 7 Table 7: Legend of 68-pin VHDCI-type connectors .... - Page 8 Figures Figure 1: PCB Layout of DAQ-22XX......... 15 Figure 2: PCB Layout of PXI-22XX........16 Figure 3: Connector CN1 pin assignment......18 Figure 4: Connector CN2 pin assignment......19 Figure 5: Floating source and RSE input connections ..22 Figure 6: Ground-referenced sources and NRSE input connections ............
- Page 9 Figure 25: Re-triggered waveform generation with Post-trigger and DLY2_Counter = 0..... 44 Figure 26: Finite iterative waveform generation with Post-trigger and DLY2_Counter = 0..... 45 Figure 27: Infinite iterative waveform generation with Post-trigger and DLY2_Counter = 0..... 46 Figure 28: Stop mode I............47 Figure 29: Stop mode II............
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Page 10: How To Use This Guide
How to Use This Guide This manual is designed to help you use/understand the DAQ/PXI-22XX. The manual des cribes the versatile functions and the operation theory of the DAQ/PXI-22XX. It is divided into five chapters: Chapter 1, “Introduction,” gives an overview of the product features, applications, and specifications. -
Page 12: Chapter 1 Introduction
Introduction The DAQ/PXI-22XX is an advanced data acquisition card based on the 32-bit PCI architecture. High performance designs and the state-of-the-art technology make this card ideal for data logging and signal analysis ap- plications in medical, process control, etc. Features DAQ/PXI-22XX Advanced Data Acquisition Card provides the following advanced features:... - Page 13 • Programmable gain DAQ/PXI-2204: x1, x2, x4, x5, x8, x10, x20, x40, x50, x200. DAQ/PXI-2205/2206: x1, x2, x4, x8. • A/D FIFO size: 1024 samples • Versatile trigger sources: software trigger, external digital trigger, analog trigger and trigger from System Synchronization Interface (SSI) •...
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Page 14: Applications
Applications • Automotive Testing • Cable Testing • Transient signal measurement • • Laboratory Automation • Biotech measurement Specifications ♦ Analog Input (AI) • Number of channels: (programmable) 64 single-ended (SE) 32 differential input (DI) Mixing of SE a nd DI analog signal sources (Software selectable per channel) •... -
Page 15: Table 1: Programmable Input Range
• Programmable input range: Device Bipolar input range Unipolar input range ±10V ±5V 0~10V ±2.5V 0~5V ±2V 0~4V ±1.25V 0~2.5V 2204 ±1V 0~2V ±0.5V 0~1V ±0.25V 0~0.5V ±0.2V 0~0.4V ±0.05V 0~0.1V ±10V 0~10V ±5V 0~5V 2205 ±2.5V 2206 0~2.5V ±1.25V 0~1.25V Table 1: Programmable input range •... -
Page 16: Table 2: -3Db Small Signal Bandwidth
• -3dB small signal bandwidth: (Typical, 25°C) Device Input range Bandwidth (-3dB) ±10V ±5V 0~10V 2000kHz ±2.5V 0~5V ±1.25V 0~2.5V ±2V 0~4V 2204 1450kHz ±0.5V 0~1V ±1V 0~2V 990kHz ±0.25V 0~0.5V ±0.2V 0~0.4V 240kHz ±0.05V 0~0.1V ±10V 0~10V 1600kHz ±5V 0~5V 1400kHz 2205... -
Page 17: Table 3: System Noise
• System Noise (LSBrms, including Quantization, Typical, 25°C) Input Device System Noise Input Range System Noise Range ±10V 0.95 LSBrms 0~10V 1.5 LSBrms ±5V 1.0 LSBrms 0~5V 1.6 LSBrms 2205 ±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms ±1.25V 1.3 LSBrms 0~1.25V 1.9 LSBrms ±10V 0.8 LSBrms... -
Page 18: Table 6: Settling Time To Full-Scale Step
• Settling time to full-scale step: (Typical, 25°C) Device Input Range Condition Settling time ±10V ±5V 0~10V Multiple channels, ±2.5V 0~5V multiple ranges. 1us to 0.1% error ±2V All samples in Unipolar 0~4V OR Bipolar mode ±1.25V 0~2.5V ±0.5V 0~1V ±10V ±5V 0~10V... - Page 19 • Time-base source: Internal 40MHz or External clock Input (f 40MHz, f : 1MHz, 50% duty cycle) • Trigger modes: post-trigger, delay-trigger, pre-trigger and mid- dle-trigger • Offset error: Before calibration: ±60mV max After calibration: ±1mV max • Gain error: Before calibration: ±0.6% of output max ±0.03% of output max for DAQ/PXI-2204 After calibration:...
- Page 20 • Output range: ±10V, 0~10V, ±AOEXTREF, 0~AOEXTREF • Settling time: 3µS to 0.5LSB accuracy • Slew rate: 20V/uS • Output coupling: DC • Protection: Short-circuit to ground • Output impedance: 0.1Ω. max. • Output driving: ±5mA max. • Stability: Any passive load, up to 1500pF •...
- Page 21 • Synchronous Digital Inputs (SDI): For DAQ/PXI-2204 only • Number of channels: 4 digital inputs sampled simultaneously with the analog signal input. • Compatibility: TTL/CMOS • Input voltage: Logic Low: VIL=0.8 V max.; IIL=0.2mA max. High: VIH=2.0V max.; IIH=0.02mA max ♦...
- Page 22 ♦ Digital Trigger (D.Trig) • Compatibility: TTL/CMOS • Response: Rising or falling edge • Pulse Width: 10ns min ♦ System Synchronous Interface (SSI) • Trigger lines: 7 ♦ Stability • Recommended warm-up time: 15 minutes • On-board calibration reference: Level: 5.000V Temperature coefficient: ±2ppm/°C Long-term stability: 6ppm/1000Hr ♦...
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Page 23: Software Support
Software Support ADLINK provides versatile software drivers and packages for users’ dif- ferent approach to building up a system. ADLINK not only provides pro- gramming libraries such as DLL for most Windows based systems, but also ® provide drivers for other software packages such as LabVIEW All software options are included in the ADLINK CD. -
Page 24: Pcis-Ocx: Activex Controls
1.4.3 PCIS-OCX: ActiveX Controls We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use PCIS-OCX ActiveX control component librar- ies for developing applications. PCIS-OCX is designed for Windows 98/NT/2000. For more detailed information about PCIS-OCX, please refer to the user's guide in the CD. -
Page 25: Chapter 2 Installation
Installation This chapter describes how to install the DAQ/PXI-22XX. The contents of the package and unpacking information that you should be aware of are outlined first. The DAQ/PXI-22XX performs an automatic configuration of the IRQ, and port a ddress. Users can use software utility, PCI_SCAN to read the system configuration. -
Page 26: Unpacking
Unpacking Your DAQ/PXI-22XX SERIES card contains electro-static sensitive com- ponents that can be easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. -
Page 27: Pci Configuration
Figure 2: PCB Layout of PXI-22XX PCI Configuration Plug and Play: As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. -
Page 28: Chapter 3 Signal Connections
Signal Connections This chapter describes the connectors of the DAQ/PXI-22XX, and the signal connection between the DAQ/PXI-22XX and external devices. Connectors Pin Assignment DAQ/PXI-22XX is equipped with two 68-pin VHDCI-type connectors (AMP-787254-1). It is used for digital input / output, analog input / output, and timer/counter signaling, etc. -
Page 29: Figure 3: Connector Cn1 Pin Assignment
AI0 (AIH0) 1 35 (AIL0) AI32 AI1 (AIH1) 2 36 (AIL1) AI33 AI2 (AIH2) 3 37 (AIL2) AI34 AI3 (AIH3) 4 38 (AIL3) AI35 AI4 (AIH4) 5 39 (AIL4) AI36 AI5 (AIH5) 6 40 (AIL5) AI37 AI6 (AIH6) 7 41 (AIL6) AI38 AI7 (AIH7) 8 42 (AIL7) AI39 AI8 (AIH8) 9... -
Page 30: Figure 4: Connector Cn2 Pin Assignment
DA0OUT 1 35 AOGND DA1OUT 2 36 AOGND AOEXTREF 3 37 AOGND NC 4 38 NC DGND 5 39 DGND EXTWFTRIG 6 40 DGND EXTDTRIG 7 41 DGND SSHOUT 8 42 SDI0 / DGND* RESERVED 9 43 SDI1 / DGND* RESERVED 10 44 SDI2 / DGND* AFI1 11... -
Page 31: Table 7: Legend Of 68-Pin Vhdci-Type Connectors
Legend: Signal Name Reference Direction Description Analog ground for AI. All three ground references (AIGND, AOGND, and AIGND -------- -------- DGND) are connected together on board Analog Input Channels 0~63. Each channel pair,AI<i, i+32> (I=0..31) can be configured either two single-ended AI<0..63>... -
Page 32: Analog Input Signal Connection
Analog Input Signal Connection The DAQ/PXI-22XX provides up to 64 single-ended or 32 differential analog input channels. You can fill the Channel Gain Queue to get desired combination of the input signal types. The analog signal can be converted to digital value by the A/D converter. To avoid ground loops and obtain a more accurate measurement from the A/D conversion, it is quite important to understand the signal source type and how to choose the analog input modes: RSE, NRSE, and DIFF mode. -
Page 33: Figure 5: Floating Source And Rse Input Connections
Referenced Single-ended (RSE) Mode In referenced single-ended mode, all the input signals are connected to the ground provided by the DAQ/PXI-22XX. It is suitable for connections with floating signal sources. Figure 5 shows an illustration. Note that when more than two floating sources are connected, these sources will be referenced to the same common ground. -
Page 34: Differential Input Mode
3.2.2.2 Differential input mode The differential input mode provides two inputs that respond to signal voltage difference between them. If the signal source is ground-referenced, the differential mode can be used for the common-mode noise rejection. Figure 7 shows the connection of ground-referenced signal sources under differential input mode. -
Page 35: Chapter 4 Operation Theory
Operation Theory The operation theory of the functions on the DAQ/PXI-22XX is described in this chapter. The functions include the A/D conversion, D/A conversion, Digital I/O and General Purpose Counter / Timer. The operation theory can help you understand how to configure and program the DAQ/PXI-22XX. A/D Conversion When using an A/D converter, users should firs t know about the properties of the signal to be measured. -
Page 36: Daq/Pxi-2204 Ai Data Format
4.1.1 DAQ/PXI-2204 AI Data Format 4.1.1.1 Synchronous Digital Inputs (for DAQ/PXI-2204 only) When each AD conversion is completed, the 12-bit converted digital data accompanied with 4 bits of SDI<3..0> from CN2 will be latched into the 16-bit register and data FIFO, as shown in Fig 9 and Fig 10. Therefore, users can simultaneously sample one analog signal with four digital signals. -
Page 37: Table 8: Bipolar Analog Input Range And The Output Digital
Table 8 and 9 illustrate the ideal transfer characteristics of some input ranges. Description Bipolar Analog Input Range Digital code Full-scale Range ±10V ±5V ±2.5V ±1.25V Least significant bit 4.88mV 2.44mV 1.22mV 0.61mV FSR-1LSB 9.9951V 4.9976V 2.4988V 1.2494V 7FFX Midscale +1LSB 4.88mV 2.44mV 1.22mV 0.61mV 001X Midscale... -
Page 38: Daq/Pxi-2205/2206 Ai Data Format
4.1.2 DAQ/PXI-2205/2206 AI Data Format The data format of the acquired 16-bit A/D data is 2’s Complement coding. Table 10 and 11 shows the valid input ranges and the ideal transfer characteristics. Description Bipolar Analog Input Range Digital code Full-scale ±10V ±5V ±2.5V... -
Page 39: Software Conversion With Polling Data Transfer Acquisition Mode (Software Polling)
4.1.3 Software conversion with polling data transfer acquisition mode (Software Polling) This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available. -
Page 40: Programmable Scan Acquisition Mode
4.1.4 Programmable scan acquisition mode 4.1.4.1 Scan Timing and Procedure It's recommended that this mode be used if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least 4 counters, which need to be specified: SI_counter (24 bit): Specify the Scan Interval = SI_counter / Timebase... -
Page 41: Figure 11: Scan Timing
3 Scans, 4 Samples per scan (PSC_Counter=3, NumChan_Counter=4) ( channel sequences are specified in Channel Gain Queue) C h 3 C h 0 Scan_start AD_conversion Scan_in_progress ( SSHOUT )(pin8 on CN2) Acquisition_in_progress Sampling Interval t= Scan Interval T= SI2_COUNTER/TimeBase SI_COUNTER/TimeBase Figure 11: Scan Timing There are 4 trigger modes to start the scan acquisition, please refer to 4.1.4.3 for the details. -
Page 42: Specifying Channels, Gains, And Input Configurations In The
Scan with SSH You can send the SSHOUT signal on CN2 to an external S&H circuits to sample and hold all signals if you want to simultaneously sample all channels in a scan, as illustrated in fig 11. Note: The ‘SSHOUT’ signal is sent to external S&H circuits to hold the analog signal. -
Page 43: Trigger Modes
4.1.4.3 Trigger Modes DAQ/PXI-22XX provides 3 trigger sources (internal software, external analog and digital trigger sources). You must select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source (For example, a rising edge on the external digital trigger input). -
Page 44: Figure 13: Pre-Trigger (Trigger With Scan Is In Progress)
Note that if a trigger event occurs when a scan is in progress, the data acquisition won’t stop until the scan completes, and the stored M scans of data includes the last scan. Therefore, the first stored data will always be the first channel entry of a scan (that is, the first channel entry in the Channel Gain Queue if the number of entries in the Channel Gain Queue is equivalent to the value of NumChan_counter), no matter when a... -
Page 45: Figure 14: Pre-Trigger With M_Enable = 0
(M_Counter = M = 3 , NumChan_Counter=4, PSC_Counter=0) Trigger Scan_start AD_conversion Scan_in_progress (SSHOUT)(pin8 on CN2) Acquisition_in_progress Acquired & stored data (2 scans) Operation start Figure 14: Pre-trigger with M_enable = 0 (trigger occurs before M scans) (M_counter = M = 3, NumChan_counter=4, PSC_counter=0) The first M scans Trigger signals which occur in the shadow region(the first M scans) will be ignored... -
Page 46: Figure 16: Middle Trigger With M_Enable = 1
Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified by M_counter, while the number of scans (N) after the trigger is specified by PSC_counter. Like pre-trigger mode, the number of stored data could be fewer than the specified amount of data (NumChan_counter *(M+N)) if an external trigger occurs before M scans of data are converted. -
Page 47: Figure 17: Middle Trigger
(M_Counter=M=2, NumChan_Counter=4, PSC_Counter=N=2) Trigger occurs when a scan is in progress Trigger Scan_start AD_conversion Scan_in_progress ( SSHOUT )(pin8 on CN2) Acquisition_in_progress Acquired data M scans before N scans trigger after trigger Operation start Acquired & stored data (M+N scans) Figure 17: Middle trigger (trigger occurs when a scan is in progress) Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data... -
Page 48: Figure 19: Delay Trigger
Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collecting process after the occurrence of a specified trigger event. The delay time is controlled by the value, which is pre-loaded in the De- lay_counter (16bit). -
Page 49: Bus-Mastering Dma Data Transfer
data. The process repeats until the specified amount of re-trigger signals are detected. The total acquired data length = NumChan_counter * PSC_counter * Retrig_no. (NumChan _Counter=4, PSC_Counter=2, retrig_no=3) Trigger Scan_start AD_conversion Scan_in_progress (SSHOUT )(pin8 on CN2) Acquisition_in_progress Acquired & stored data (6 scans) Operation start Figure 20: Post trigger with retrigger... -
Page 50: Figure 21: Scatter/Gather Dma For Data Transfer
of conversion into their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus -mastering DMA. The PCI controller also supports the function of scatter/gather bus mas- tering DMA, which helps the users to transfer large amounts of data by linking all the memory blocks into a continuous linked list. -
Page 51: D/A Conversion
D/A Conversion There are 2 channels of 12-bit D/A output available in the DAQ/PXI-22XX. When using D/A converters, users should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels. Users could also select the output polarity: unipolar or bipolar. The reference selection control lets users fully utilize the multiplying characteristics of the D/A converters. -
Page 52: Software Update
The D/A conversion is initiated by a trigger source. Users must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met. Before the start of D/A conversion, D/A data is transferred from PC’s main memory to a buffering Data FIFO. There are two modes of the D/A conversion: Software Update and Timed Waveform Generation are described, including timing, trigger source con- trol, trigger modes and data transfer methods. -
Page 53: Figure 22: Typical D/A Timing Of Waveform Generation
4 update counts, 3 iterations (UC _Counter=4, IC_Counter=3) Trigger UC_Counter=4 DAWR WFG_in_progress Delay until Delay until Delay until DLY1_Counter DLY2_Counter DLY2_Counter reaches 0 reaches 0 reaches 0 DA update_interval t= UI_Counter/Timebase Output Waveform Operation start A single waveform IC_Counter = 3 Figure 22: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) Note: The maximum D/A update rate is 1MHz. -
Page 54: Trigger Modes
4.2.2.1 Trigger Modes Post-Trigger Generation Use post trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1_Counter is not used and you don’t need to specify it. Figure 23 shows a single waveform generated right after a trigger signal is detected. -
Page 55: Figure 24: Delay Trigger Waveform Generation
8 update counts, 1 iteration (UC _Counter=8, IC_Counter=1) Trigger DAWR WFG_in_progress Output Waveform Delay until DLY1_counter reaches 0 Operation start Figure 24: Delay trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. -
Page 56: Iterative Waveform Generation
4.2.2.2 Iterative Waveform Generation Set IC_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number, and the itera- tions could be finite (Figure 26) or infinite(Figure 27). Note that in infinite mode the waveform generation won’t stop until software stop function is executed, and IC_Counter is still meaningful when stop mode III is selected. -
Page 57: Stop Modes Of Scan Update
4 update counts, infinite iterations (UC _Counter=4, IC_Counter=3) Trigger waveform generation won’t stop until software stop function is DAWR executed WFG_in_progress Output Waveform Operation start Figure 27: Infinite iterative waveform generation with Post-trigger and DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) Delay2 in iterative Waveform Generation To stretch out the flexibility of the D/A waveform generation, we add a DLY2 Counter to separate 2 consecutive waveforms in iterative waveform... -
Page 58: Figure 28: Stop Mode I
In stop mode III, after a software stop command is given, the waveform generation won’t stop until the performed number of waveforms is a mul- tiple of IC_Counter. See figure 30 for an example, since IC_Counter is set to 3, the total generated waveforms must be a multiple of 3 (waveforms = 6 in this example), and the total DA update counts must be a multiple of 12 (UC_Counter * IC_Counter). -
Page 59: Digital I/O
4 update counts, infinite iterations (UC _Counter=4, IC_Counter=3) Trigger DAWR WFG_in_progress Output Waveform Operation start Software stop command Figure 30: Stop mode III Digital I/O DAQ/PXI-22XX contains 24-lines of general-purpose digital I/O (GPIO), which is provided through a 82C55A chip. The 24-lines GPIO are separated into three ports: Port A, Port B and Port C. -
Page 60: General Purpose Timer/Counter Operation
General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are designed within FPGA for various applications. They have the following features: • Count up/down controlled by hardware or software • Programmable counter clock source (internal or external clock up to 10MHz) •... -
Page 61: Mode1: Simple Gated-Event Counting
4.4.2.1 Mode1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC_CLK after the software-start. Initial count can be loaded from software. Current count value can be read-back by software any time without affecting the counting. -
Page 62: Mode 3: Single Pulse-Width Measurement
4.4.2.3 Mode 3: Single Pulse-width Measurement In this mode the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is in its active state. -
Page 63: Mode5: Single Triggered Pulse Generation
4.4.2.5 Mode5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro- grammable pulse-width following an active GPTC_GATE edge. You could specify these programmable parameters in terms of periods of the GPTC_CLK input. Once the first GPTC_GATE edge triggers the single pulse, GPTC_GATE takes no effect until the software-start is re-executed. -
Page 64: Mode7: Single Triggered Continuous Pulse Generation
4.4.2.7 Mode7: Single Triggered Continuous Pulse Generation This mode is similar to mode5 except that the counter generates con- tinuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC_GATE. Once the first GPTC_GATE edge triggers the counter, GPTC_GATE takes no effect until the soft- ware-start is re-executed. -
Page 65: Trigger Sources
Trigger Sources We provide flexible trigger selections in the DAQ/PXI-22XXseries products. In addition to the internal software trigger, DAQ/PXI-22XX also supports external analog, digital triggers and SSI triggers. Users can configure the trigger source by software for A/D and D/A processes individually. Note that the A/D and the D/A conversion share the same analog trigger. -
Page 66: Below-Low Analog Trigger Condition
Trigger Level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V 0x81 0.08V 0x80 0x7F -0.08V 0x01 -9.92V Table 14: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic The trigger signal is generated when the analog trigger condition is satis- fied. There are five analog trigger conditions in DAQ/PXI-22XX. DAQ/PXI-22XX uses 2 threshold voltages: Low_Threshold and High_ Threshold to build the 5 different trigger conditions. -
Page 67: Above-High Analog Trigger Condition
4.5.2.2 Above-High analog trigger condition Figure 41 shows the above-high analog trigger condition, the trigger signal is generated when the input analog signal is higher than the High_Threshold voltage, and the Low_Threshold setting is not used in this trigger condition. Figure 41: Above-High analog trigger condition 4.5.2.3 Inside-Region analog trigger condition... -
Page 68: High-Hysteresis Analog Trigger Condition
4.5.2.4 High-Hysteresis analog trigger condition Figure 43 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High_Threshold voltage, and the Low_Threshold voltage determines the hysteresis duration. Figure 43: High-Hysteresis analog trigger condition 4.5.2.5 Low-Hysteresis analog trigger condition Figure 44 shows the low-hysteresis analog trigger condition, the trigger... -
Page 69: External Digital Trigger
4.5.3 External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXTDTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger. The EXTDTRIG is dedicated for A/D process, and the EXTWFTRG is used for D/A process. -
Page 70: User-Controllable Timing Signals
User-controllable Timing Signals In order to meet the requirements for user-specific timing and the r e - quirements for synchronizing multiple cards, the DAQ/PXI-22XX series provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ/PXI-22XX series is composed of a bunch of counters and trigger signals in the FPGA. -
Page 71: Daq Timing Signals
4.6.1 DAQ timing signals The user-controllable DAQ timing-signals contains: (Please refer to 4.1.4.1 for the internal timing signal definition) TIMEBASE, providing TIMEBASE for all DAQ operations, which could be from internal 40MHz oscillator, EXTTIMEBASE from I/O connector or the SSI_TIMEBASE. Note that the frequency range of the EXTTIMEBASE is 1MHz to 40MHz, and the EXTTIMEBASE should be TTL-compatible. -
Page 72: Table 15: Auxiliary Function Input Signals And The
Summary of the auxiliary function input signals and the corresponding functionalities Category Timing signal Functionality Constraints 1. TTL-compatible Replace the 2. 1MHz to 40MHz EXTTIMEBASE internal 3. Affects on both A/D and TIMEBASE D/A operations 1. TTL-compatible External digital Dedicated 2. - Page 73 EXTDTRIG and EXTWFTRIG EXTDTRIG and EXTWFTRIG are dedicated digital trigger input signals for A/D and D/A operations respectively. Please refer to section 4.5.3 for de- tailed descriptions. EXTTIMEBASE When the applications needs specific sampling frequency or update rate that the card could not generate from its internal TIMEBASE, the 40MHz clock, users could utilize the EXTTIMEBASE with internal counters to achieve the specific timing intervals for both A/D and D/A operations.
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Page 74: System Synchronization Interface
AFI[1] Regarding the D/A operations, users could directly input the external D/A update signal to replace the internal DAWR signal. This is another way to achieve customized D/A update rates. The external DAWR signal can only be inputted from the AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can only be utilized for one function at any one time. - Page 75 In PCI form factor, there is a connector on the top right corner of the card for the SSI. Refer to section 2.3 for the connector position. All the SSI sig- nals are routed to the 20-pin connector from the FPGA. To synchronize multiple cards, users can connect a special ribbon cable (ACL-SSI) to all the cards in a daisy-chain configuration In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane...
- Page 76 When the digital trigger condition of Card 1 occurs, Card 1 will internally generate the ADCONV signal and output this ADCONV signal to SSI_ADCONV signal of Card 2, 3 and 4 through the SSI/PXI connectors. Thus we can achieve 16-channel acquisition simultaneously. You could arbitrarily choose each of the 6 timing signals as the SSI master from any one of the cards.
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Page 77: Chapter 5 Calibration
Calibration This chapter introduces the calibration process to minimize AD meas- urement errors and DA output errors. Loading Calibration Constants The DAQ/PXI-22XX is factory calibrated before shipment by writing the associated calibration constants of TrimDACs to the on-board EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability. -
Page 78: Auto-Calibration
Auto-calibration By using the auto-calibration feature of the DAQ/PXI-22XX, the calibration software can measure and correct almost all the calibration errors without any external signal connections, reference voltages, or measurement de- vices. The DAQ/PXI-22XX has an on-board calibration reference to ensure the accuracy of auto-calibration. -
Page 79: Warranty Policy
Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the fo llowing carefully. Before using ADLINK’s products, please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form. - Page 80 . Damaged products with RMA forms attached receive priority. For further questions, please contact our FAE staff. ADLINK: service@adlinktech.com Test & Measurement Product Segment: NuDAQ@adlinktech.com Automation Product Segment: Automation@adlinktech.com Computer & Communication Product Segment: NuPRO@adlinktech.com NuIPC@adlinktech.com Warranty Policy • 69...
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