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Cronologic TimeTagger4 User Manual

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TimeTagger4
User Guide
w w w. c r o n o l o g i c . d e

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Summary of Contents for Cronologic TimeTagger4

  • Page 1 TimeTagger4 User Guide w w w. c r o n o l o g i c . d e...

  • Page 2: Table Of Contents

    4.5.3 Structure timetagger4_tiger_block ......GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 3 ........8.1.1 TDC measurement Characteristics for Gen 1 TimeTagger4 .
  • Page 4 Erratum GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 5: Introduction

    The TimeTagger4 is a common-start low resolution high throughput time-to-digital converter. Time- stamps of leading or trailing edges (or both) of digital pulses are recorded. The TimeTagger4 produces a stream of output packets, each containing data from a single start event. The relative timestamps of all stop pulses that occur within a configurable range are grouped into one packet.

  • Page 6: Applications

    1.2 Applications The TimeTagger4 can be used in all time measurement applications where a common-start setup with 100 ps resolution is sufficient. For alternatives with higher resolution, more channels or higher readout rates check our TDC website www.cronologic.de. The TimeTagger4 is well suited for the following applications: •...

  • Page 7: Hardware

    2.1 Installing the PCIe Board The TimeTagger4 board can be installed in any PCIe-CEM slot with x1 or more lanes. Make sure that the PC is powered off and that the main power connector is disconnected while installing the board.
  • Page 8 TiGer. Furthermore, for Gen 1 boards three inter-board connectors can be found near the top edge of the TimeTagger4 board, as displayed in Figure 2.4. Connector J25 is reserved for future use. The pinout of connector J12 is shown in Table and the pinout of connector J6 is depicted in Table 2.2.
  • Page 9 29, 30 31, 32 reserved/NC 33, 34 Pinout of connector J12. Table 2.1 Name +3 . 3 V 2 - 9 reserved/NC Pinout of connector J6. Table 2.2 GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 10: Status Leds Of The Pcie Boards

    • LED2 lights up green after the board is initialized by the driver and turns off when the device is closed by the software. • LED3 lights up green when capture is started, yellow after the first start signal was detected and red when groups are missing. GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 11: Timetagger4 Functionality

    Triggers on the start channel must not occur less than 5 ns apart. The TimeTagger4 records events without dead time at a readout rate of about 48 MHits/s for Gen 1 and 60 MHits/s for Gen 2.

  • Page 12: Auto-Triggering Function Generator

    ] − 1 clock cycles with a duration of 4 ns per cycle for Gen 1 and 3 . 2 ns for Gen 2 TimeTagger4. The standard values of M = 62500 and N = 0 result in a frequency of 4 kHz for TimeTagger4 Gen 1 and 5 kHz for ≤...

  • Page 13: Calibration Of The 10G Variant

    TimeTagger4 and the external hardware. Pulses that are short enough for the input AC coupling are available as input signals to the TimeTagger4. This can be used to measure exact time differences between the generated output signals and input sig- nals on other channels.
  • Page 14 • Repeat this process for channels B, C, and D, as well. After a successful calibration of the TimeTagger4-10G, the message “Calibrated all channels success- fully” will be displayed. You can close the calibration tool. In case the calibration fails, please check the following: •...

  • Page 15: Driver Programming Api

    All these files are provided with the driver installer that can be downloaded from the product website www.cronologic.de. By default, the installer will place the files into the directory C:\Program Files\ cronologic\TimeTagger4\driver . A coding example can be found on github.com/cronologic-de/xtdc_babel.

  • Page 16: Initialization

    The minimum size of the DMA buffer. If set to 0 the default size of 16 MByte is used. For the TimeTagger4, only the first entry is used. buffer_type The type of buffer. Must be set to 0 .

  • Page 17: Status Information

    Set to 0 . Can be used to activate future device variants such as different base frequencies. device_type A constant for the different devices of cronologic CRONO_DEVICE_* . Initialized by timetagger4_get_default_init_parameters() . This value is identical to the PCI Device ID. Must be left unchanged.

  • Page 18: Structure Timetagger4_Static_Info

    API. driver_build_revision Build number of the driver according to cronologic’s internal versioning system. firmware_revision Revision number of the FPGA configuration.

  • Page 19: Structure Timetagger4_Param_Info

    If not 0 , the driver found valid calibration data in the flash on the board and is using it. This value is not applicable for the TimeTagger4. char calibration_date[20] DIN EN ISO 8601 string YYYY-MM-DD HH:MM of the time when the card was calibrated.

  • Page 20: Structure Timetagger4_Fast_Info

    The total amount of DMA buffer in bytes. double packet_binsize For the TimeTagger4 the packet binsize is equal to the binsize and depends on the generation of the card. Gen 1 boards have a packet binsize of 500 ps, while Gen 2 boards have 100 ps. double quantisation Quantisation or measurement resolution.

  • Page 21: Structure Crono_Pcie_Info

    Alert bits from the temperature sensor and the system monitor. The TimeTagger4 does not implement any temperature alerts. pcie_pwr_mgmt Always 0 . pcie_link_width Number of PCIe lanes the card uses. Should always be 10 for the TimeTagger4. pcie_max_payload Maximum size in bytes for one PCIe transaction. Depends on system configuration.

  • Page 22: Configuration

    This is the structure containing the configuration information. It is used in conjunction with timetagger4_get_default_configuration() , timetagger4_get_current_configuration() and timetagger4_configure() . It uses multiple substructures to configure various aspects of the board. size The number of bytes occupied by the structure. version GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 23 (respecting the different periods or can be set to maximum of 0xFFFFFFFF ), if all events need to be captured. crono_bool_t start_rising Not applicable for the TimeTagger4. Rising and/or falling edge are configured using the timetagger4_trigger structure (see Section 4.5.2). double dc_offset[TIMETAGGER4_TDC_CHANNEL_COUNT + 1] Set the threshold voltage for the input channels S, A …D (see Figure 4.1).
  • Page 24 Create a trigger either periodically or randomly. There are two parameters M = auto_trigger_period N = random_exponent that result in a distance between triggers of T clock cycles. GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 25: Structure Timetagger4_Trigger

    If enabled the timer is reset to the value of the start parameter, whenever the input signal is set while waiting to reach the stop time. crono_bool_t extend Not implemented. GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 26: Structure Timetagger4_Channel

    In multiples of 4 ns for Gen 1 and 3 . 2 ns for Gen 2 TimeTagger4. The time during which the TiGer output is set, relative to the trigger input. The parameters start and stop must fulfill the following conditions 0 ≤...

  • Page 27: Structure Timetagger4_Delay_Config

    4.5.5 Structure timetagger4_delay_config Contains configurable delay value for TimeTagger4 Gen 2 (see Section 3.4). uint32_t delay Delay in static_info.delay_bin_size (currently 200 ps) for a channel. The possible values are the following 0 ≤ delay ≤ 1023 GmbH & Co. KG TimeTagger4 –...

  • Page 28: Run Time Control

    // automatically acknowledge all data as processed in.acknowledge_last_read = 1; volatile crono_packet* p = read_data.first_packet; timetagger4_read_out out; status = timetagger4_read(device, &in, &out); (status == CRONO_READ_OK) { while (p <= read_data.last_packet) { processPacket(p); p = crono_next_packet(p); GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 29: Input Structure Timetagger4_Read_In

    Assignments of the error codes. #define CRONO_READ_OK #define CRONO_READ_NO_DATA #define CRONO_READ_INTERNAL_ERROR #define CRONO_READ_TIMEOUT const char *error_message The last error in human-readable form, possibly with additional information about the error. GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 30: Output Data Format

    The data stream consists of 32-bit unsigned data as signified by CRONO_PACKET_TYPE_32_BIT_UNSIGNED = 6 . uint8_t flags Bit field of TIMETAGGER4 _PACKET_FLAG_* bits: #define TIMETAGGER4_PACKET_FLAG_ODD_HITS 1 If this bit is set, the last data word in the data array consists of one timestamp only which is located in the lower 32 bits of the 64-bit data word (little endian).
  • Page 31 = (hit >> 4) & 0xF; uint32_t channel & 0xF; Bits 7 down to 4 are hit flags and have the following definitions: • Bit 7: Not applicable for the TimeTagger4 and therefore always 0 . #define TIMETAGGER4_HIT_FLAG_COARSE_TIMESTAMP 4 ↔ Bit 6 •...

  • Page 32: Code Example

    7 Code Example The following C++ source code shows how to initialize a TimeTagger4 board, configure it and loop over incoming packets. If you are reading this documentation in portable document format (PDF), the source code of the C example is also embedded as an attachment to the file.
  • Page 33 // sending a signal to the LEMO outputs (and to the TDC on the same channel) // requires proper 50 Ohm termination on the LEMO output to work reliably GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 34 // optionally increase input delay by 10 * 200 ps for each channel on new TT // config.delay_config[i].delay = i * 10; // write configuration to board return timetagger4_configure(device, &config); GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 35 // be empty // This flag tells us, whether the number of hits in the packet is odd ((p->flags & TIMETAGGER4_PACKET_FLAG_ODD_HITS) != 0) hit_count -= 1; uint32_t* packet_data = (uint32_t*)(p->data); GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 36 %c - flags %d - offset %u (raw) / %.1f ns ↩ \n", channel_letter, flags, ts_offset, ts_offset_ns); return group_abs_time; int main(int argc, char* argv[]) { printf("cronologic timetagger4_user_guide_example using driver: %s\n", timetagger4_get_driver_revision_str()); GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 37 = false; int64_t group_abs_time = 0; int64_t group_abs_time_old = 0; update_count = 100; printf("Reading packets:\n"); bool no_data_printed = false; // read 10000 packets while (packet_count < 10000) GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 38 = packet_count % update_count == 0; processPacket( p, print, &static_info, &parinfo); no_data_printed = false; p = crono_next_packet(p); packet_count++; // shut down packet generation and DMA transfers timetagger4_stop_capture(device); // deactivate timetagger4 timetagger4_close(device); return GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 39: Technical Data

    Each board is tested against the values listed in the columns “Min” and “Max”. “Typical” is the mean value of the first 10 boards produced or a value that is set by design. 8.1 TDC Characteristics 8.1.1 TDC measurement Characteristics for Gen 1 TimeTagger4 Symbol Parameter...

  • Page 40: Tdc Measurement Characteristics For Gen 2 Timetagger4

    8.1.2 TDC measurement Characteristics for Gen 2 TimeTagger4 Symbol Parameter Typical Units Integral non-linearity bins Differential non-linearity –1.25G to –5G 0.01 Data –10G Data format bin size Data Quantization Quant –1.25G –2.5G –5G –10G Double pulse resolution Quant Measurement range using hits only 1.677...

  • Page 41: Electrical Characteristics

    12.9 PCIe 12 V rail input current PCIe 3.3 V rail power supply voltage PCIe 3.3 V rail input current 8.2.2 TDC Inputs The TimeTagger4’s inputs are single-ended AC-coupled with 50 Ω termination. Symbol Parameter Typical Units Input Baseline Base −...

  • Page 42: Information Required By Din En 61010-1

    8.3.2 Intended Use and System Integration The devices are not ready to use as delivered by cronologic. It requires the development of specialized software to fulfill the application of the end-user. The device is provided to system integrators to be built into measurement systems that are distributed to end users.

  • Page 43: Environmental Conditions For Operation

    9, “Überwachungs und Kontrollinstrumente für ausschließlich gewerbliche Nutzung.” The last owner of a TimeTagger4 must recycle it, treat the board in compliance with §11 and §12 of the German ElektroG, or return it to the manufacturer’s address listed on Page 42.

  • Page 44: Ordering Information

    PCIe: PCIe CEM x1 plugin board 1.25G: 1.25 Gsps / 800 ps binsize 2.5G: 2.5 Gsps / 400 ps binsize 5G: 5 Gsps / 200 ps binsize 10G: 10 Gsps / 100 ps binsize GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 45: Revision History

    2021-06-23 Fixed register write issues 0.983 2019-03-15 Internal optimizations 0.971 2019-02-19 Hit sorting and packet generation issues fixed 10.2 Firmware Gen 2 Revision Date Comments 0.23180 2023-06-29 Initial release GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...

  • Page 46: Driver & Applications

    1.9.3 2024-07-16 xHPTDC8: Fix driver revision list xHPTDC8: Added LED documentation 1.9.2 2024-07-09 TimeTagger4 and xTDC4: Add overview figure of TBT and PCIe variant Fixed grammar 1.9.1 2024-07-02 xHPTDC8: Updated firmware list Added new driver revision TimeTagger4 and xTDC4: Added TBT variant 1.9.0...
  • Page 47 Revision Date Comments TimeTagger4: Added documentation for 10G calibration tool xTDC4 and TimeTagger4: Added LED documentation 1.8.16 2024-06-20 xHPTDC8: Fixed default values for zero_channel Clarifications for TiGer block indices Fixed auto_trigger formula Updated oscillator characteristics 1.8.15...
  • Page 48 Revision Date Comments 1.3.0 2019-06-05 API clarifications GmbH & Co. KG TimeTagger4 – User Guide, Rev. 1.9.3 cronologic...
  • Page 49 Erratum We found undesired behavior for Gen 1 devices of the TimeTagger4. If there are three or more edges close together (within 6 . 6 ns) and the user did only enable rising or falling edges but not both, some edges are reported with the wrong polarity.

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