1. Manuals
  2. Brands
  3. Cronologic Manuals
  4. Computer Hardware
  5. Ndigo5G-PCIe
  6. User manual

Cronologic Ndigo5G-PCIe User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Ndigo5G-PCIe
USER GUIDE
www.cronologic.de

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Ndigo5G-PCIe and is the answer not in the manual?

Questions and answers

Related Manuals for Cronologic Ndigo5G-PCIe

Summary of Contents for Cronologic Ndigo5G-PCIe

  • Page 1 Ndigo5G-PCIe USER GUIDE www.cronologic.de...

  • Page 2: Table Of Contents

    ....... . GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 3 6.3.2 Intended Use and System Integration ......GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 4 ..........GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 5: Introduction

    • 2 digital input for gating or triggering • PCIe 4x 1.1 with 800 MB/s throughput • possibility to synchronize multiple boards • extension board with four additional digital inputs GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 6: Hardware

    Ndigo Crate user guide. In applications that use only a few Ndigo boards installed directly inside a PC, termination PCBs available from cronologic can be used. Ndigo5G’s standard device driver can be used to read out all boards and acquire data. For more complex scenarios, using the cronoSync-library, which is part of cronoTools, is recommended.

  • Page 7: Ndigo5G External Inputs And Connectors

    The analog inputs of the ADC are single ended LEMO00 coax connectors. The inputs have a 50Ω impedance and are AC coupled. The inputs are converted to a differential signal using a balun. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 8 (see Figure 2.6). By shifting the DC baseline to one end of the ADC range, the input range can be used fully, providing the maximum dynamic range. The analog offset can be set between ± 0 , 25V . GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 9: Digital Inputs

    AC coupled inputs support NIM signaling. The signals connect to 2.5V IO Pins of the Xilinx Virtex-5 FPGA. The current firmware revision provides the following signal connections. The HPTDC clocks are 5 GHz / 128 = 39 . 0625 MHz GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 10: Ndigo5G Functionality

    Data processing such as trigger detection or packet building are always performed on 3.2ns intervals. Depending on the ADC mode, this interval may contain 4, 8 or 16 samples. The board supports using one, two or four channels: GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 11 1.25 Gsps 1.25 Gsps 1.25 Gsps 1.25 Gsps (2.5 GHz) circuit AAI, AAIN BAI, BAIN CAI, CAIN DAI , DAIN ADCs in 4 channel mode ABCD at 1.25Gsps. Figure 2.7 GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 12 1.25 Gsps 1.25 Gsps 1.25 Gsps In-phase Inverted 1.25 GHz 1.25 GHz AAI,,AAIN,or,BAI,BAIN,or,CAI ,,CAIN,or,DAI ,,DAIN ADCs in 1 channel mode A, B, C or D interleaved for Figure 2.9 5Gsps. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 13: Zero Suppression

    When using edge triggering, all packets have the same length (Figure 2.11 length + 1 cycles of 3.2ns. For level triggering, packet length is data dependent (Figure 2.12 on page GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 14 This procedure reduces PCIe bus load even further (Figure 2.20). total length = 19 precursor = 6 length = 12 Parameters for edge triggering Figure 2.11 GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 15 Figure 2.13 clock cycle. total length = 4 precursor = 1 length = 2 3200 ps Triggering in 2 channel mode at 8 samples per Figure 2.14 clock cycle. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 16 Each digitizer channel (A, B, C, D) has two trigger units. input rising edge The digital inputs Trigger, GATE, BUS0, BUS1, Figure 2.17 BUS2 and BUS3 have simpler trigger units. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 17 Trigger input, the GATE input or the sync cable can be combined to create a trigger input for each trigger block. The four gate signals can be used to suppress triggers during certain time frames. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 18: Gating Blocks

    The parameters of a gating block are set in Structure ndigo_gating_block described on page 35. Figure 2.21 shows the functionality of the gate timing and delay unit. Active gate time is marked in green. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 19 (see fig. 2.22): a falling level trigger with an upper threshold and a rising level trigger with a lower threshold. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 20 . t r i g g e r [ NDIGO_TRIGGER_A1 ] . t h r e s h o l d = −10000; GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 21: Auto Triggering Function Generator

    32 bit pattern that contains the levels of all trigger sources at the time of the trigger event except for the period monitor. Only one packet is created, no matter how many trigger sources caused the timestamp channel to trigger. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 22: Data Lookup Table

    (LUT) which needs to be provided by the user. This is done by defining the corresponding function as a custom_lut-member of the ndigo_configuration structure. Please feel free to contact cronologic if you plan the use this feature. The onboard INL correction is applied prior to mapping the LUT values.

  • Page 23: Calibration Procedure

    Therefore, a Ndigo250M board only needs to be calibrated as a slave. 6. After finding all delay values, write the values to the on-board flash PROMs by pressing “Flash All!”. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 24 Histogram for the case the delay value for the Figure 2.26 board is set correctly. Please note: the lower panel might differ from board to board, with the “step” being at a different position. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 25: Synchronizing A Ndgio5G And An Hptdc8-Pci

    Ndigo5G device driver. CronoSync offers an easy group-based access to the data recorded and handles the synchronization of all cronologic data ac-quisition devices used. A detailed description of cronoTools and cronoSync can be found in the cronoTools user guide.

  • Page 26: Calibrating The Tdc

    Input Offset value for a successful calibration may be in the range of 6 – 10 or 28 – 32. 5. When the Write Calibration Data button becomes enabled press it to update the calibration data on the card. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 27 • at least 10,000 events have been captured • a valid serial number is set. If the application reports an error, check if the input pulse is within specification. Important note: GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 28: Driver Programming Api

    This index selects one of them. Boards are enumerated depending on the PCIe slot. The lower the bus number and the lower the slot number the lower the card index. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 29 #define CRONO_DEVICE_NDIGO250M 2 dma_read_delay Initialized by ndigo_get_default_init_parameters(). The write pointer update is delay by this number of 4 ns clock periods to hide race conditions between software and DMA. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 30: Status Information

    A change in the first digit generally requires a recompilation of user applications. Change in the second digit denote significant improvements or changes that don’t break compatibility and the third digit GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 31 Serial number with the year minus 2000 in the highest 8 bits of the integer and a running number in the lower 24 bits. This number is identical with the one on the label on the board. flash_serial_low flash_serial_high 64 bit manufacturer serial number of the flash chip. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 32: Structure Ndigo_Param_Info

    Set to 0 for all versions up to first release. adc_rpm Speed of the ADC fan. Reports 0 if no fan is present. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 33: Structure Ndigo_Slow_Info

    ROM , than modify the structure as needed for the user application and use the result to configure the device. int ndigo_get_default_configuration(ndigo_device *device, ndigo_configuration *config) int ndigo_get_current_configuration(ndigo_device *device, ndigo_configuration *config) GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 34: Structure Ndigo_Configuration

    The bandwidth of the analog frontend of the board remains unchanged at about 950 MHz. ndigo_bool_t reserved ndigo_bool_t tdc_enabled Enable capturing of TDC measurements on external digital input channel. ndigo_bool_t tdc_fb_enabled GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 35 Enable output drive for each of the four external sync lines. Each integer represents a bitmask selecting the trigger sources for that line. The bit mapping is described in section “Structure ndigo_trigger_block” on page 33. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 36: Structure Ndigo_Trigger

    For trigger indices NDIGO_TRIGGER_TDC to NDIGO_TRIGGER_BUS3_PE the threshold is ignored. ndigo_bool_t edge If set this trigger implements edge trigger functionality else this is a level trigger. For trigger indices NDIGO_TRIGGER_AUTO and NDIGO_TRIGGER_ONE this is ignored. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 37: Structure Ndigo_Trigger_Block

    The length setting is ignored for the timestamp channel. sources A bit mask with a bit set for all trigger sources that can trigger this channel. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 38 The on-board algorithm checks the free FIFO space only in case the FIFO is full. Therefore, if this number is 1.0 or more at least every second packet in the DMA buffer is guaranteed to GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 39: Structure Ndigo_Gating_Block

    A bit mask with a bit set for all trigger sources that can trigger this channel. The gates cannot use the additional digital trigger sources NDIGO_TRIGGER_SOURCE_TDC_PE to NDIGO_TRIGGER_SOURCE_BUS3_PE. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 40: Structure Ndigo_Extension_Block

    Ndigo extension board is used. 3.4.6 Run Time Control int ndigo_start_capture(ndigo_device *device) int ndigo_pause_capture(ndigo_device *device) int ndigo_continue_capture(ndigo_device *device) Call this to resume data acquisition after a call to ndigo_pause_capture. int ndigo_stop_capture(ndigo_device *device) GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 41: Readout

    There is no blue component in the current version. Per default all LEDs are set to auto mode. This means that used channels are lit green, activity is shown as yellow on overflow is shown as red. int ndigo_set_led_color(ndigo_device *device, led, unsigned short unsigned short unsigned short GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 42 Set the LED to the selected color. No automatic updates are performed. int ndigo_set_led_automode(ndigo_device *device, led) Let the selected LED be controlled by hardware. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 43: Packet Format

    NDIGO_PACKET_FLAG_HOST_BUFFER_FULL 32 If the bit with weight 32 is set, the host buffer was full. Triggers only got lost if a subsequent package has the bit with weight 8 set. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 44 For the Ndigo5G, each 64 bit word contains four 16 bit signed words from the ADC. The user can cast the array to short* to directly operate on the sample data. GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 45: Example

    ( −1) ; n d i g o _ s t a r t _ c a p t u r e ( ndgo ) ; GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...
  • Page 46 = ndigo_next_packet ( packet ) ; ndigo_acknowledge ( ndgo , packet ) ; packet = next_packet ; count ++; ndigo_close ( ndgo ) ; r e t u r n 0 ; GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 47: Technical Data

    Signal to Noise Ration SFDR Spurious Free Dynamic Range (including Harmonics) incl SFDR Spurious Free Dynamic Range (excluding Harmonics) excl SINAD2 Signal-to-Interference Ratio including Noise and Distortion ENOB2 Effective Number of Bits GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 48: 4-Channel-Mode (1.25 Gsps)

    6.2.3 Environmental Conditions for Storage The board shall be stored between operation under the following conditions: Symbol Parameter Typical Units ∘ ambient temperature –30 ∘ relative humidity at 31 C non condensing GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 49: Power Supply

    Single ended AC coupled inputs Trigger and GATE with configurable DC offset bias. Symbol Parameter Typical Units Pulse height trig DC offset –1.25 1.25 trigoffset DC offset for TDC –1.25 –0.01 tdcoffset input impedance Ω trig pulse width pulse GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 50: Information Required By Din En 61010-1

    6.3.2 Intended Use and System Integration The devices are not ready to use as delivered by cronologic. It requires the development of specialized software to fulfill the application of the end user. The device is provided to system integrators to be built into measurement systems that are distributed to end users.

  • Page 51: Known Bugs

    Workarounds Use Ndigo6G All other cronologic products work reliably in Thunderbolt enclosures. The Ndigo6G offers very similar functionality to the Ndigo5G at a higher performance. When using the Ndigo6G as a replacement, there are some software changes required in the device configuration. The readout data format and API is identical.

  • Page 52: Revision History

    Fixed broken backup in firmware tool and display errors in NdigoScope 1.4.3 2019-10-21 Fixed a card initialization error in x64 32 mode 1.4.0 2019-06-04 Added Windows 10 support 1.3.0 2017-06-08 NdigoScope application now supports Ndigo250M-14 GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

  • Page 53: User Guide

    Corrected extension card clock from 39 MHz to 39.0625 MHz Analog Bandwidth clarifications and corrections 1.2.1 2020-09-20 Cosmetic changes 1.1.3 2020-11-27 Dual-Use information 1.1.2 2019-10-27 1.1.0 2019-08-27 API clarifications GmbH & Co. KG Ndigo5G-10 – User Guide, Rev. 1.2.3 cronologic...

Table of Contents