1. Manuals
  2. Brands
  3. NPM Manuals
  4. Computer Hardware
  5. PCL6115
  6. User manual

NPM PCL6115 User Manual

Pulse control lsi
Hide thumbs Also See for PCL6115:
Table of Contents

Advertisement

Quick Links

Download this manual
DA70152-1/0E1
Pulse Control LSI
PCL6115 / 6125 / 6145
User's Manual

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PCL6115 and is the answer not in the manual?

Questions and answers

Related Manuals for NPM PCL6115

Summary of Contents for NPM PCL6115

  • Page 1 DA70152-1/0E1 Pulse Control LSI PCL6115 / 6125 / 6145 User's Manual...
  • Page 2 DA70152-1/0E1 [Preface] Thank you for considering our pulse control LSI, the "PCL6100 series." Before using the product, please read this manual to become familiar with it. Please note that the section "Handling Precautions", which includes the details of installing these ICs, is shown at the end of this manual.

  • Page 3: Table Of Contents

    3. Hardware description .................................. 7 3.1 External dimensions ................................7 3.2 Terminal assignment diagrams ............................13 3.3 Terminal list ..................................16 3.3.1 PCL6115 ..................................16 3.3.2 PCL6125 ..................................21 3.3.3 PCL6145 ..................................29 3.4 Block Diagram ..................................40 3.5 CPU bus interface ................................41 3.5.1 Parallel bus interface ..............................
  • Page 4 DA70152-1/0E1 5. Operation Mode ..................................106 5.1 Command control ................................106 5.1.1 Positive direction continuous movement operation mode (MOD: 00h) ............... 106 5.1.2 Negative direction continuous movement operation mode (MOD: 08h) ..............106 5.2 Positioning control ................................107 5.2.1 Incremental movement operation mode (MOD: 41h) ....................107 5.2.2 Timer operation mode (MOD: 47h) ..........................
  • Page 5 7.14 ID Monitor ..................................186 8. Electrical Characteristics................................. 187 8.1 Absolute maximum ratings ..............................187 8.2 Recommended operating conditions ..........................187 8.3 DC characteristics ................................188 8.3.1 PCL6115 ..................................188 8.3.2 PCL6125 ..................................189 8.3.3 PCL6145 ..................................190 - C3 -...
  • Page 6 DA70152-1/0E1 8.4 AC characteristics ................................191 8.4.1 Reference Clock ................................. 191 8.4.2 16-bit interface-1 (68000, etc.) ............................ 192 8.4.3 16-bit interface-2 (H8, etc.) ............................195 8.4.4 16-bit interface-3 (8086, etc.) ............................198 8.4.5 8-bit interface (Z80, etc.) ............................. 201 8.4.6 Serial interface ................................204 8.5 Operation timing (common for all axes)..........................

  • Page 7: Outline And Features

    The number of control axes is; one for the PCL6115, two for the PCL6125, and four for the PCL6145. The operation status of LSI can be monitored from the CPU, and the LSI can output interrupt signals per a variety of conditions.
  • Page 8 DA70152-1/0E1 Linear acceleration/deceleration sections can be inserted in the middle of an S-curve acceleration/deceleration curve by S- curve section settings. The S-curve sections can be set differently between acceleration and deceleration. If the S-curve section is extremely short, such as setting the S-curve section to 1 pps or less, it will appear to be linear acceleration/deceleration.
  • Page 9 DA70152-1/0E1 ♦ Comparators There are 4 comparator circuits for each axis. They can be used to compare target values and internal counter values. Comparator 1 can be compared with COUNTER 1 and Comparator 2 can be compared with COUNTER 2. Comparator 3 and 4 are for software limit function only.
  • Page 10 DA70152-1/0E1 ♦ Origin return sequences A variety of origin return controls can be selected by setting of the start command and the optional operation mode bit. <Examples of origin return sequences> 1) An operation starts at constant speed, and stops immediately when ORG signal turns ON 2) An operation starts at constant speed and stops immediately when a specified number of encoder Z-phase signals is counted after ORG signal turns ON.
  • Page 11 DA70152-1/0E1 ♦ Output pulse mode You can select from common pulse mode, 2-pulse mode and 90-degree phase difference mode. The logic can also be selected. ♦ Emergency stop signal (CEMG) When this signal turns ON, all axes will stop immediately. If this signal is ON at start, the axis will not start.

  • Page 12: Specification

    3.0 to 3.6 V (External dimensions 14 × 14 mm, Mold part 12 × 12 mm) Package PCL6115: 80-pin QFP (External dimensions 16 × 16 mm, Mold part 14 × 14 mm) PCL6125: 128-pin QFP (External dimensions 26 × 26 mm), Mold part 24 × 24 mm)

  • Page 13: Hardware Description

    The following parts explains the hardware such as external dimensions and terminal layouts. 3.1 External dimensions We will explain the external dimensions of each model: 1. PCL6115 P C L 6 1 1 5 J A P A N - 7 -...
  • Page 14 DA70152-1/0E1 Dimension in mm Name Min. Nom. Max. 11.90 12.00 12.10 11.90 12.00 12.10 13.60 14.00 14.40 13.60 14.00 14.40 □ e 0.50 0.13 0.20 0.27 0.08 A max 0.00 0.10 0.20 1.30 1.40 1.50 0.30 0.50 0.75 0.80 1.00 1.20 θ...
  • Page 15 DA70152-1/0E1 2. PCL6125 PCL6125 JAPAN - 9 -...
  • Page 16 DA70152-1/0E1 Dimension in mm Name Min. Nom. Max. 13.90 14.00 14.10 13.90 14.00 14.10 15.60 16.00 16.40 15.60 16.00 16.40 □ e 0.40 0.13 0.18 0.23 0.08 A max 1.70 0.00 0.10 0.20 1.30 1.40 1.50 0.30 0.50 0.75 0.80 1.00 1.20 θ...
  • Page 17 DA70152-1/0E1 3. PCL6145 PCL6145 JAPAN - 11 -...
  • Page 18 DA70152-1/0E1 Dimension in mm Name Min. Nom. Max. 23.90 24.00 24.10 23.90 24.00 24.10 25.60 26.00 26.40 25.60 26.00 26.40 □ e 0.50 0.17 0.22 0.27 0.08 A max 1.70 0.00 0.10 0.20 1.30 1.40 1.50 0.30 0.50 0.75 0.80 1.00 1.20 θ...

  • Page 19: Terminal Assignment Diagrams

    DA70152-1/0E1 3.2 Terminal assignment diagrams The following shows the terminal assignments of each LSI. 1. PCL6115 58 56 54 52 48 46 44 42 O UT ← □ □ ← PCS DI R ← □ □ ← ALM ERC ← □...
  • Page 20 DA70152-1/0E1 2. PCL6125 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 P7y ⇔ □ □ → ERCx VDD － □ □ → DI Rx O UTy ← □ □ → O UTx DI Ry ←...
  • Page 21 DA70152-1/0E1 3. PCL6145 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 O RGu → □ □ － VDD ALM u → □ □ ⇔ P3y/CP1y PCSu → □ □...

  • Page 22: Terminal List

    The output terminals of all signals can be pulled up to +5 V. However, equal to or more than VDD cannot be output. (Equal to or more than 5k ohm resistant value is recommended.) 3.3.1 PCL6115 Terminal No. Signal name...
  • Page 23 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description WRQ/MISO Parallel bus interface: Outputs a wait request signal. Serial bus interface: Outputs the input data to CPU. Parallel bus interface: Outputs an interface busy signal. Serial bus interface: Leave it Open. Power supply terminal.
  • Page 24 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description Inputs a slow-down signal. See “7.4.2 Slow-down signal (SDn)” for details. Inputs an origin position signal. See “7.4.3 Origin position signal (ORGn), encoder Z-phase signal (EZn)” for details. Inputs an alarm signal input from a servo motor driver. See “7.5.3 Alarm signals (ALMn)”...
  • Page 25 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description P0/FUP P0 terminal used for a general-purpose I/O port or an output (PD) terminal for on-going acceleration signals. See “4.4.4.3 RENV2: Environment setting 2 register” for details. P1/FDW P1 terminal used for a general-purpose I/O port or an output (PD) terminal for on-going slow-down signals.
  • Page 26 DA70152-1/0E1 Terminal Signal name Direction Logic Handling Description Inputs the reference clock (CLK) signal. Standard frequency is 19.6608 MHz. Power supply terminal Connects to GND. Power supply terminal Connects to GND. (GND) Input terminal for shipping inspection. Connects to GND. Power supply terminal Connects to 3.3 V.

  • Page 27: Pcl6125

    DA70152-1/0E1 3.3.2 PCL6125 Terminal No. Signal name Direction Logic Handling Description IF0/SCK Parallel bus interface: Sets CPU bus interface mode. Serial bus interface: Inputs a serial clock signal. IF1/MOSI Parallel bus interface: Sets CPU bus interface mode. Serial bus interface: Inputs I/O data from CPU. Power supply terminal Connects to 3.3 V.
  • Page 28 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description D4/GP4 Parallel bus interface: Connect data bus; Bit 4 to Bit 7. D5/GP5 (PD) Serial bus interface: Become shared I/O ports; GP4 to GP7 D6/GP6 terminals. D7/GP7 Power supply terminal Connects to 3.3 V. D8/GP8 Parallel bus interface: Connect 16-bit data bus;...
  • Page 29 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description LTCx Inputs a counter latch signal. See “7.10.2 Latch and clear (LTCn)” for details. Power supply terminal Connects to GND. Inputs A-phase signals from an encoder. See “7.10.1 Counter type and input specification” for details. Inputs B-phase signals from an encoder.
  • Page 30 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description P5 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details. P6 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details. P7 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register”...
  • Page 31 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description Inputs a slow-down signal. See “7.4.2 Slow-down signal (SDn)” for details. Inputs an origin position signal. ORGy See “7.4.3 Origin position signal (ORGn), encoder Z-phase signal (EZn)” for details. Inputs an alarm signal input from a servo motor driver. ALMy See “7.5.3 Alarm signals (ALMn)”...
  • Page 32 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description P0y/FUPy P0 terminal used for a general purpose I/O port or an output (PD) terminal for on-going acceleration signal. See “4.4.4.3 RENV2: Environment setting 2 register” for details. P1y/FDWy P1 terminal used for a general purpose I/O port or an output (PD) terminal for on-going slow-down signal.
  • Page 33 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description MVCy Outputs constant speed signals. It becomes L level during constant speed operation. CP1y Outputs a signal when the condition of comparator 1 is met. It becomes L level while the condition of comparator 1 is met. CP2y Outputs signal when the condition of comparator 2 is met.
  • Page 34 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description ELLy Selects the input logic for end limit signal. L level (GN): Input logic is positive. H level (+V): Input logic is negative. Inputs a reset signal. See “7.1 Reset” for details. Power supply terminal Connects to GND.

  • Page 35: Pcl6145

    DA70152-1/0E1 3.3.3 PCL6145 Terminal No. Signal name Direction Logic Handling Description IF0/SCK Parallel bus interface: Sets CPU bus interface mode. Serial bus interface: Input a serial clock signal. IF1/MOSI Parallel bus interface: Sets CPU bus interface mode. Serial bus interface: I/O data from CPU. Power supply terminal Connects to 3.3 V.
  • Page 36 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description D4/GP4 Parallel bus interface: Connect data bus; Bit 4 to Bit 7. D5/GP5 (PD) Serial bus interface: Become shared I/O ports; GP4 to GP7 D6/GP6 terminals. D7/GP7 Power supply terminal Connects to 3.3 V. D8/GP8 Parallel bus interface: Connect 16-bit data bus;...
  • Page 37 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description LTCx Inputs counter latch signals. See “7.10.2 Latch and clear (LTCn)” for details. Power supply terminal. Connects to GND. Inputs A-phase signals from an encoder. See “7.10.1 Counter type and input specification” for details. Inputs B-phase signals from an encoder.
  • Page 38 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description P5 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details. P6 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details.
  • Page 39 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description LTCy Input counter latch signals See “7.10.2 Latch and clear (LTCn)” for details. Power supply terminal. Connects to 3.3 V. Inputs A-phase signals from an encoder. See “7.10.1 Counter type and input specification” for details. Inputs B-phase signals from an encoder.
  • Page 40 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description P5 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details. P6 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details P7 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register”...
  • Page 41 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description LTCz Input a counter latch signal. See “7.10.2 Latch and clear (LTCn) for details. Power supply terminal. Connects to GND. Inputs A-phase signals from an encoder. See “7.10.1 Counter type and input specification” for details. Inputs B-phase signals from an encoder.
  • Page 42 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description P5 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details. P6 terminal used for a general purpose I/O port (PD) See “4.4.4.3 RENV2: Environment setting 2 register” for details.
  • Page 43 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description LTCu Input a counter latch signal. See “7.10.2 Latch and clear (LTCn)” for details. Power supply terminal. Connects to 3.3 V. Inputs A-phase signals from an encoder. See “7.10.1 Counter type and input specification” for details. Inputs B-phase signals from an encoder.
  • Page 44 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description P4u/CP2u P4 terminal used for a general purpose I/O port or an output terminal for a signal that indicates the condition of comparator 2 is met. See “4.4.4.3 RENV2: Environment setting 2 register” for details.
  • Page 45 DA70152-1/0E1 Terminal No. Signal name Direction Logic Handling Description CSTA Inputs/outputs a simultaneous start signal. See “7.6.1 Simultaneous start signal (CSTA)” for details. CSTP Inputs/outputs a simultaneous stop signal. See “7.8.1 Simultaneous stop signal (CSTP)” for details. CEMG Inputs an emergency stop signal. See “7.9.1 Emergency stop signal (CEMG)”...

  • Page 46: Block Diagram

    DA70152-1/0E1 3.4 Block Diagram CS/SS, RD, WR, INT, IFB, WRQ/MISO CEMG CSTA, CSTP, CSD IF0/SCK, IF1/MOSI CPU bus I/F All axes A0/DS0, A1/DS1 - A4 (Built-in bus switch circuit) controller D0/GP0 - D15/GP15 RFL, RFH, RUR, RDR Magnification Linear Pulse width OUTx, DIRx divider interporator...

  • Page 47: Cpu Bus Interface

    DA70152-1/0E1 3.5 CPU bus interface This LSI contains a total of 5 types of interface circuit: 4 types of parallel bus interface circuit and 1 type of serial bus interface circuit, making it easier to connect to a variety of CPUs. 3.5.1 Parallel bus interface This section explains the CPU settings and the CPU connections when the parallel bus interface is selected.
  • Page 48 Connects A0 to LDS for all LSI models. The following terminals are connected to the addresses of CPU. PCL6145: A1 to A4, PCL6125: A1 to A3, PCL6115: A1 and A2. For 16-bit interface, word-size-access (16-bit) is available, but byte-size-access (8-bit) is not available.
  • Page 49 Connects A0 to GND for all LSI models. The following terminals are connected to the addresses of CPU: PCL6145: A1 to A4, PCL6125: A1 to A3, PCL6115: A1 and A2. For 16-bit interface, word-size-access (16-bit) is available, but byte-size-access (8-bit) is not available.

  • Page 50: Serial Bus Interface

    DA70152-1/0E1 3.5.2 Serial bus interface In this chapter, we will explain CPU settings and CPU connections when a serial bus interface is selected. 3.5.2.1 Connecting CPU settings When both RD terminal and WR terminal are in L level at the rising edge of reset signal, it becomes parallel bus interface. [Example of serial bus interface CPU signal connection] Settings Connecting CPU signal...

  • Page 51: Software Description

    In this LSI, the control address range for each axis is independent. It is selected by using address input terminal; A4 and A3 as follows. Detail PCL6145, PCL6125 (A3 terminal only), PCL6115 (without A3 and A4 X-axis control address range terminals)
  • Page 52 DA70152-1/0E1 4.1.1.1.2.2 16-bit interface-3 1) Write cycle Address Processing description name COMW Write axis selections and commands. Change statuses of general-purpose output ports (only the bits assigned as outputs OTPW are enabled) BUFW0 Write to I/O buffer (bits 15 to 0) BUFW1 Write to I/O buffer (bits 31 to 16) 2) Read cycle...
  • Page 53 Settings from SELx to SELu are effective for all commands. PCL6145 can select from SELx to SELu; PCL6125 can select SELx and SELy. However, PCL6115 ignores writing to COMB1 address. For 8-bit interface, write “command codes” to COMB 0 address after writing “axis selection code” to COMB 1 address.
  • Page 54 DA70152-1/0E1 4.1.1.2.1.2 Writing procedures When writing commands consecutively, waiting time of 4 reference clock frequency cycles (approximately 0.2 μs) is required between commands. When WRQ signal is available with CPU, the CPU automatically secures the waiting time. When WRQ signal is not available with CPU, make sure to secure this waiting time of 4 reference clock frequency cycles or longer with software.
  • Page 55 DA70152-1/0E1 Writing registers 4.1.1.2.2.1 I/O buffer (BUF) “Data to write to the registers”, is written to BUFW0 and BUFW1 addresses. BUFW1 BUFW0 BUFB3 BUFB2 BUFB1 BUFB0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUFW1 (BUFB3, BUFB2): Set the upper data.
  • Page 56 DA70152-1/0E1 2. Writing commands is conducted in the common area; only writing I/O buffer is conducted in individual area of each axis. So, the axis needs to be selected when writing all commands. Since data is written to the same registers of axes selected by one command at one time, the data setting time can be shortened.
  • Page 57 DA70152-1/0E1 Reading registers 4.1.1.2.3.1 I/O buffer (BUF) “Register data” is read from BUFW0 and BUFW1 addresses. BUFW1 BUFW0 BUFB3 BUFB2 BUFB1 BUFB0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUFW1 (BUFB3, BUFB2): Obtain the upper data.
  • Page 58 DA70152-1/0E1 Reading main-status 4.1.1.2.4.1 Main-status(MSTS) “Main-status”(MSTS) is read from MSTSW address. MSTSW MSTSB1 MSTSB0 MSTS MSTSW (MSTSB1, MSTSB0): “MSTS” is obtained. For the detais of “MSTS”, see “4.2.1 Main-status (MSTS)”. 4.1.1.2.4.2 Reading procedures 1) Read “MSTS” from MSTSB1, MSTSB0 addresses. No particular order for reading.
  • Page 59 DA70152-1/0E1 Writing general-purpose output ports 4.1.1.2.5.1 General-purpose output port (OTP) “General-purpose output port”(OTP) is written to OTPW address. OTPW OTPB OTPW.OTPB: Sets “OTP”. Set the status of general-purpose I/O terminals (P7 to P0) that have been specified to be output. H level is output when “1”...
  • Page 60 DA70152-1/0E1 Reading sub status and general-purpose I/O ports 4.1.1.2.6.1 Sub-status (SSTS) and general-purpose I/O port(IOP) Sub-status (SSTS) and general purpose I/O port (IOP) are read from SSTSW address. SSTSW SSTSB IOPB SSTS SSTSW.SSTSB: “SSTS” is obtained. SSTSW.IOPB: “IOP” is obtained. On “SSTS”...

  • Page 61: Serial Communication

    DA70152-1/0E1 4.1.2 Serial communication The format of serial communication and the access method are as follows. 4.1.2.1 Communication format The writing format (MOSI) consists of “Axis selection (SEL)”, “Command (COM)” and “Data (DAT)”. “Axis selection (SEL)” must be included. “Commands (COM)” and “Data (DAT)” may not be included depending on the access method. The numbers of “data (DAT)”...
  • Page 62 PCL6145 SELu SELz SELy SELx PCL6125 SELy SELx PCL6115 SELx Commands(COM) It consists only of “Command code”. Command code See “4.3 Commands” for details. Data (DAT) It consists of various numbers of “data” depending on the axis selection code. The selected axes are arranged by X, Y, Z, and U order.
  • Page 63 DA70152-1/0E1 <Register writing data> They are arranged from X-axis to U-axis in 4-byte unit. Each axis is arranged from low byte to high byte. If writing data is less than 4 bytes, 00h is required for the insufficient byte. (12345h → 45h, 23h, 01h, 00h) Each byte is arranged from MSB to LSB.
  • Page 64 DA70152-1/0E1 4.1.2.2 Access method Writing commands, writing registers, reading registers, reading main-statuses, writing general-purpose output ports, and reading sub statuses & general-purpose I/O ports can be done using communication format. Note: 1. If you interrupt control (SS signal becomes H level in the middle of writing) without writing the number of bits as specified in format, unexpected data is written.
  • Page 65 DA70152-1/0E1 4.1.2.2.2. Writing registers 4.1.2.2.2.1 Axis selection, Command, Data (Register) Write “Axis selection” and “Commands” by writing command format. “Data” is written as well. DATx DATy DATz DATu Same Same Same MOSI: S7 to S0 C7 to C0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 DATx DATx DATx...
  • Page 66 DA70152-1/0E1 Reading register 4.1.2.2.3.1 Axis selection, Commands, Data (Register) Write “Axis selection” and “Command” by writing command format. MOSI: S7 to S0 C7 to C0 Read “Data”. DATx DATy DATz DATu MISO: D7 to D0 D15 to D8 D23 to D16 D31 to D24 Same as DATx Same as DATx...
  • Page 67 DA70152-1/0E1 Reading Main-status 4.1.2.2.4.1 Axis selection, Data (MSTS) Write “Axis selection” by main-status reading format. MOSI: S7 to S0 Read “MSTS”. DATx DATy DATz DATu MISO: D7 to D0 D15 to D8 Same as DATx Same as DATx Same as DATx SEL: Set “Device selection code”, “Type selection code”...
  • Page 68 DA70152-1/0E1 Writing general-purpose output port 4.1.2.2.5.1 Axis selection, Data (OTP) Write “Axis selection” by general-purpose output port writing format, and write “OTP” as well. DATx DATy DATz DATu MOSI: S7 to S0 D7 to D0 Same as DATx Same as DATx Same as DATx SEL: Set “Device selection code”, “Type selection code”...
  • Page 69 DA70152-1/0E1 Read sub status and general-purpose I/O port 4.1.2.2.6.1 Axis selection, Data (SSTS, IOP) Write “Axis selection” by sub status reading format. MOSI: S7 to S0 Read “SSTS” and “IOP”. DATx DATy DATz DATu MISO: D7 to D0 D15 to D8 Same as DATx Same as DATx Same as DATx...

  • Page 70: Status

    DA70152-1/0E1 4.2 Status The status during parallel communication will be updated whenCLK signal is input once or more during “RD = H level”. 4.2.1 Main-status (MSTS) Reads operation status, interrupt type, comparator and pre-register status. MSTSW MSTSB1 MSTSB0 SPRF SEOR SCP4 SCP3 SCP2 SCP1 SSC1 SSC0 SINT SERR SEND SENI SRUN SSCM Name...
  • Page 71 DA70152-1/0E1 Name Description Not defined It is always “0”. Name Details 0: Stopping at target position or operating. 1: Stopping at other than target position. It occurs when writing to the RMV register in the stopped state (the target position override has not SEOR been executed) and when RPLS >...
  • Page 72 DA70152-1/0E1 3. Continuous movement by switch control (RMD.MOD = 02h): START STOP MSTS SSCM SRUN SENI SEND 4. Stopped by positioning control such as incremental movement (RMD.MOD = 41h) START MSTS SSCM SRUN SENI SEND - 66 -...

  • Page 73: Sub Status (Ssts) And General-Purpose I/O Ports (Iop)

    DA70152-1/0E1 4.2.2 Sub status (SSTS) and general-purpose I/O ports (IOP) Read the signal statuses of input terminals, the acceleration/deceleration statuses during operations and the signal statuses of general purpose I/O terminals. SSTSW SSTSB IOPB SORG SMEL SPEL SALM IOP7 IOP6 IOP5 IOP4 IOP3...

  • Page 74: Command

    DA70152-1/0E1 4.3 Command 4.3.1 Operation commands Start and stop the operation modes. 4.3.1.1 Start command An operation starts if this command is written while stopped. If written during an operation, it becomes the start command for the following operation. Name Description STAFL Start operations with the speed pattern of FL constant speed start.
  • Page 75 DA70152-1/0E1 4.3.1.4 Speed change commands It can be used in the operation mode of command control continuous movement (RMD.MOD = 00h, 08h) or positioning control incremental movement (RMD.MOD = 41h). If these commands are written during operations, the axis changes its target speed and speed pattern. Commands written while stopping are ignored.

  • Page 76: General-Purpose Output Bit Control Commands

    DA70152-1/0E1 4.3.2 General-purpose output bit control commands Controls P0 to P7 terminals that are set as general-purpose output terminals per 1 bit. The command for the terminal corresponding to general-purpose input terminal is ignored. When controlling all 8-bit at a time, write to general output port. See "4.1.1.2.5 Write to general-purpose output port”...

  • Page 77: Control Commands

    DA70152-1/0E1 4.3.3 Control commands 4.3.3.1 Software reset command Name Description Resets LSI with software. SRST After writing this command, wait for access for 12 cycles of CLK signal (0.6 μs). 4.3.3.2 Counter clear command Sets “0” in the counter. Name Description CUN1R Clear COUNTER 1 (RCUN1).
  • Page 78 DA70152-1/0E1 4.3.3.7 SENI, SEOR clear command This command clears each bit of the main-status (MSTS) manually. It is used when “RENV2.MRST = 1” (write manual clear). Name Description SENIR Clear stop interrupt bit (MSTSW.SENI). SEORR Clear bit that shows stop other than target position (MSTS.SEOR). 4.3.3.8 ID code confirmation command Name Description...

  • Page 79: Register Control Commands

    DA70152-1/0E1 4.3.4 Register control commands Data will be copied between register and I/O buffer by writing register control command. 4.3.4.1 Register control command list The following registers are dedicated for each axis. You can access individual dedicated registers from each axis Register Pre-register Contents...

  • Page 80: Register (Pre-Registers)

    DA70152-1/0E1 4.4 Register (Pre-registers) All registers (pre-registers) go to “0” after resetting, but “0” can be out of the setting range in some registers. The negative number representation of signed numbers is two’s complement. Except for start commands, no re-writing is required when the value to be set is the same as the last time. Several registers (pre-registers) can be written and all registers (pre-registers) can be read.
  • Page 81 DA70152-1/0E1 The following shows the relationship between writing status of pre-register and MSTS.SPRF bit: Procedure Pre-register Register SPRF Initial status while stopping. (Unfixed) (Fixed) While stopping, write data 1 to pre-register. Data 1 Data 1 Data 1 is automatically copied to register. (Unfixed) (Unfixed) Write start command.

  • Page 82: Speed Control Registers

    DA70152-1/0E1 4.4.2 Speed control registers The following are the registers for speed control. Name Description Bit length Range 16,383 RFL (PRFL) FL speed setting (3FFFh) 16,383 RFH (PRFH) FH speed setting (3FFFh) 65,535 RUR (PRUR) Acceleration rate setting (FFFFh) 65,535 RDR (PRDR) Deceleration rate setting (FFFFh)
  • Page 83 DA70152-1/0E1 4.4.2.1 RFL (PRFL): FL speed setting register It is used to set FL speed (initial speed/stop speed) for high-speed start [WPRFL: 81h, RPRFL: C1h] (acceleration/deceleration operations). PRFL is the pre-register for RFL register. [WRFL: 91h, RRFL: D1h] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Setting range: 1 to 16,383 (3FFFh) The actual FL speed [pps] is calculated with the value in RMG register.
  • Page 84 DA70152-1/0E1 4.4.2.5 RMG (PRMG): Speed magnification rate setting register It is used to set speed magnification rate. [WPRMG: 85h, RPRMG: C5h] PRMG is the pre-register for RMG register. [WRMG: 95h, RRMG: D5h] IDCD Position Name Description Setting range is 1 to 4,095. Set the relationship between set values in RFL or RFH registers and the actual speeds.
  • Page 85 DA70152-1/0E1 4.4.2.6 RDP (PRDP): Slow-down point setting register. This register sets the slow-down point to be used in incremental movement operation mode. [WPRDP: 86h, RPRDP: C6h] PRDP is the pre-register for RDP register. [WRDP: 96h, RRDP: D6h] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # # # # # # # # Bits marked with name “#”...
  • Page 86 DA70152-1/0E1 4.4.2.9 RSPD: Current speed obtaining register It is used to obtain current speed and EZ count value. [RRSPD: F5h] (Read only.) Position Name Description Current speed can be read as a step value (the same units as in RFL or RFH register). It is “0” when 13 to 0 stopping.

  • Page 87: Position Control Register

    DA70152-1/0E1 4.4.3 Position control register The following are the registers for position control operations: Name Description Bit length Range Sets feeding amount (=target position) -2,147,483,648 +2,147,483,647 RMV (PRMV) (80000000h) (7FFFFFFFh) Sets feeding amount of the main axis for 2,147,483,648 RIP (PRIP) linear interpolation (80000000h) Acquiring positioning counter (Obtain...

  • Page 88: Environment Setting Registers

    DA70152-1/0E1 4.4.4 Environment setting registers The followings are registers for environment setting: Name Description Length Range RMD (PRMD) Operation mode setting RENV1 Environment setting 1 RENV2 Environment setting 2 RENV3 Environment setting 3 RENV4 Environment setting 4 RGPM Shared I/O port management RGPD Shared I/O port information 4.4.4.1 RMD (PRMD): Operation mode setting register...
  • Page 89 DA70152-1/0E1 Position Name Description Selects input functions of INPn terminal. 0: General-purpose input. MINP INPn terminal status can be obtained by RSTS.SINP bit. 1: Operation completion is delayed until in-position signal turns ON. Selects acceleration/deceleration operations. MSMD 0: Linear acceleration/deceleration. 1: S-curve acceleration/deceleration.
  • Page 90 MAX1 0: Not select Y-axis. 1: Selects Y-axis. Selects whether to include Z-axis in the target axis when “RMD.MSY = 11b”. For PCL6115 and PCL6125, the selection is ignored. MAX2 0: Not select Z-axis. 1: Selects Z-axis. Selects whether to include U-axis in the target axis when “RMD.MSY = 11b”.
  • Page 91 DA70152-1/0E1 Position Name Description Selects triangular drive avoidance function 0: Avoid triangular drive. MADJ 1: Not avoid triangular drive. (Undefined) Always set “0”. Selects input functions of CSD terminal. You can decelerate own-axis at deceleration start of other axes. 0: General-purpose input MCDE CSD terminal status can be obtained by RSTS.SCSD bit.
  • Page 92 DA70152-1/0E1 4.4.4.2 RENV1: Environment setting 1 register Register for environment setting 1. [WRENV1: 9Ch, RRENV1: DCh] Sets mainly for I/O terminal specifications. ERCL EROR EROE ALML ALMM ORGL SDL SDLT SDM PMSK PCSM INTM DTMF DRF FLTR DRL PCSL LTCL INPL STPM STAM Position Name...
  • Page 93 DA70152-1/0E1 Position Name Description Selects slow-down signal input process. [See Note.] 0: Deceleration only. 1: Deceleration stop. Selects input latch functions of SDn terminal. It can be used when the signal width of slow-down signal is short. 0: It does not latch input of slow-down signal. Status of the SDn terminal can be obtained with RSTS.SDIN bit.
  • Page 94 DA70152-1/0E1 Position Name Description Selects ERCn terminal output logic. ERCL 0: Negative logic 1: Positive logic Selects deviation counter clear signal OFF timer time. 17, 16 00b: 0 μs, 01b: 11 to 13 μs, 10b: 1.4 to 1.6 ms, 11b: 93 to 100 ms Selects simultaneous start signal input specification.
  • Page 95 DA70152-1/0E1 Position Name Description Selects interrupt request signal output functions. 1: When an interrupt factor occurs, “INT = L level” is set. INTM 2: When an interrupt factor occurs, “INT = L level” is not set Main-status and interrupt factor register will change. Selects the functions of PCSn and STA terminals.
  • Page 96 DA70152-1/0E1 4.4.4.3 RENV2: Environment setting 2 register Register for environment setting 2. [WRENV2: 9Dh, RRENV2: DDh] Sets mainly for terminal specifications of general purpose I/O port, encoder signal input, manual pulser signal input, and origin return controls. POFF EOFF CSPO P7M MRST IEND ORM PDIR PINF EDIR EINF...
  • Page 97 DA70152-1/0E1 Position Name Description Selects the function of P6n terminals. 0: General-purpose input 1: General-purpose output. Selects the function of P7n terminals. 0: General-purpose input 1: General-purpose output Sets the function of CSTP terminal. Other axis can be stopped by stopping of own-axis by stop command. CSPO 0: A one-shot pulse with negative logic is not output when own-axis is stopped by stop command.
  • Page 98 DA70152-1/0E1 Position Name Description Selects input noise filter of PAn and PBn terminals. 0: Recognizes signals with pulse width of 0.1 μs or wider. PINF 1: Recognizes signals with pulse width of 0.15 μs or wider. Selects the counting directions of manual pulser signals (PAn, PBn). PDIR 0: Forward direction 1: Reversed direction...
  • Page 99 DA70152-1/0E1 4.4.4.4 RENV3: Environment setting 3 register Register for environment setting 3. [WRENV3: 9Eh, RRENV3: DEh] Mainly sets counter functions, latch 1 and 2 functions, comparator functions and internal synchronous signal I/O functions. C2RM CU2R LOF2 CU2L C1RM CU1R LOF1 CU1L CU2H CU1H CIS2 CIS1 SLCU Position Name...
  • Page 100 DA70152-1/0E1 Position Name Description Sets the latch function to RLTC2 register by LTCn terminal. 0: Latches counter 2 with counter latch signal input. LOF2 1: Not latch counter 2 with counter latch signal input. It can be latched by LTCH (29h) command. Counter latch signal is the edge-trigger.
  • Page 101 DA70152-1/0E1 4.4.4.5 RENV4: Environment setting 4 register Register for environment setting 4. [WRENV4: 9Fh, RRENV4: DFh] Mainly sets latch 3 and 4 functions. L4MD L4DT L4TL L3MD L3DT L3TL Position Name Description Selects the input terminal of a trigger signal to be latched in RLTC3 register. 2 to 0 000: Disable 001: LTCn terminal...
  • Page 102 DA70152-1/0E1 Position Name Description Selects the input noise filter characteristic of a trigger signal to be latched in the RLTC4 register. 00b: Recognizes a signal with a pulse width of 0.1 μs or more. 01b: Recognizes signals with a pulse width of 3.2 μs or more. 15, 14 10b: Recognizes signals with a pulse width of 25 μs or more.
  • Page 103 DA70152-1/0E1 4.4.4.6 RGPM: Shared I/O port management register Register to manage shared I/O ports. [WRGPM: BAh, RRGPM: FAh] Selects the function specifications of shared I/O ports (GP0 to GP15) that can be used with the serial bus interface. It will be ignored with pararell interface. GM15 GM14 GM13 GM12 GM11 GM10 GM9 GM6 GM5 GM4 GM3...

  • Page 104: Count Register

    DA70152-1/0E1 4.4.5 Count register The following is the registers for counters: Name Description Range length RCUN1 Counter 1(Mainly command position) -2,147,483,648 +2,147,483,647 RCUN2 Counter 2(Mainly mechanical position) -2,147,483,648 +2,147,483,647 RCMP1 Comparison data 1 -2,147,483,648 +2,147,483,647 RCMP2 Comparison data 2 -2,147,483,648 +2,147,483,647 Comparison data 3 RCMP3...
  • Page 105 DA70152-1/0E1 4.4.5.3 RCMP1: Comparison data 1 register Sets and gets status of comparison data 1. [WRCMP1: A7h, RRCMP1: E7h] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Setting range: −2,147,483,648 to +2,147,483,647 See “7.11 Comparators”...
  • Page 106 DA70152-1/0E1 4.4.5.7 RLTC1: Latch data 1 register Register to obtain latch data 1. [RRLTC1: EDh] Only for counter 1(RCUN1). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data range: –2,147,483,648 to +2,147,483,647 See “7.10.2 Latch and clear (LTCn)”...

  • Page 107: Interrupt Register

    DA70152-1/0E1 4.4.6 Interrupt register The following shows the registers for interrupt settings. Name Description Length Range RIRQ Sets event interrupt factor REST Obtains error interrupt factor RIST Obtains event interrupt factor 4.4.6.1 RIRQ: Event interrupt factor setting register Register to set and obtain the event interrupt factor setting. [WRIRQ: ACh, RRIRQ: ECh] Sets the bit corresponding to the content to generate an event interrupt to “1”.
  • Page 108 DA70152-1/0E1 Position Name Description (Undefined) Always set “0”. IRL3 1: If the count value is latched in RLTC3 register, an interrupt is generated. IRL4 1: If the count value is latched in RLTC4 register, an interrupt is generated. 31 to 18 (Undefined) Always set “0”.
  • Page 109 DA70152-1/0E1 4.4.6.3 RIST register Register to obtain the event interrupt factor [WRIST: B3h, RRIST: F3h] The corresponding bit will be “1” when an error interrupt occurs. When “RENV2.MRST = 0” is set, all bits are cleared by reading RIST register. When “RENV2.MRST = 1”...

  • Page 110: Status Indicating Register

    DA70152-1/0E1 4.4.7 Status indicating register Register to indicate status. No. Name Description Length Range RSTS Obtains extension status 4.4.7.1 RSTS: Obtaining extension status register Register to obtain extended status. [RRSTS: F1h] SINP SDIN SLTC SMDR SPDR SEZ SERC SPCS SEMG SSTP SSTA SCSD SL4F SL4C SL4E SL3F SL3C SL3E SDIR...
  • Page 111 DA70152-1/0E1 Position Name Description 1: “MDRn = L level” when “RMD.DRL = 0”. SDRM “MDRn = H level” when “RMD.DRL = 1”. 1: “LTCn = L level” when “RENV1.LTCL = 0”. SLTC “LTCn = H level” when “RENV1.LTC = 1”. 1: “SDn = L level”...
  • Page 112 DA70152-1/0E1 5. Operation Mode Sets the basic operation mode using the mode selection bit “RMD.MOD” in operation mode setting register. 5.1 Command control Writing start command starts an operation mode. Writing stop command stops an operation mode. When the output pulse mode is common pulse mode or 2-pulse mode, the direction signal changes at the time of writing the RMD register.
  • Page 113 DA70152-1/0E1 5.2 Positioning control Writing start command starts the operation mode. It stops its operation mode when it reaches the target position. Operation mode Direction of movement Positive direction when PRMV ≥ “0”. Incremental movement Negative direction when PRMV < “0”. Positive direction (“DIR terminal= H level”).
  • Page 114 DA70152-1/0E1 5.3 Manual pulser control It operates in synchronization with the input of manual pulser signals (PAn, PBn). It can be used when “PEn = L level” and “RENV2.POFF = 0”. Using PEn terminal, you can switch to use one manual pulser for multiple axes. An input noise filter of PEn terminals can be selected (RENV1.DRF).
  • Page 115 DA70152-1/0E1 When using input of 90-degree phase difference signal of 3 multiplication (RENV2.PIM = 10b) When using 2-pulse signal input. (RENV2.PIM = 11b) In synchronization with an input of manual pulser signals, internal pulse of FH speed is output intermittently. Therefore, between input of manual pulser signal and output of command pulse, an error of one internal pulse cycle can occur at the longest.
  • Page 116 DA70152-1/0E1 Input specification of manual pulser signal (PAn, PBn) <RENV2.PIM(21, 20)> [RENV2] (R/W) 00b: 90-degree phase difference mode of 1 multiplication 01b: 90-degree phase difference mode of 2 multiplication10b: 90-degree phase difference mode of - - n n - - - - 4 multiplication 11b: 2- pulse mode Counting direction of manual pulser signal (PAn, PBn)
  • Page 117 DA70152-1/0E1 5.3.1 Continuous movement operation mode (MOD: 01h) It is an operation mode to move continuously in synchronization with the input of manual pulser signals. The operation mode can be ended by writing STOP (49h) command. Setting 1 to RENV2.PDIR bit can reverse the direction of operation without changing the wiring of PAn and PBn terminals. Manual pulser signal input specification PDIR Operating direction...
  • Page 118 DA70152-1/0E1 5.4 Switch control It can be controlled by inputs of external switch signals (PDRn and MDRn). With “PEn = L level”, input of external switch signal can be used. By using PEn terminal, one set of external switches is changed to be used by multiple axes. The input noise filter for PEn terminal and PDRn, MDRn terminal can be selected (RENV1.DRF).
  • Page 119 DA70152-1/0E1 The external switch control has the following two operation modes: Operation mode Direction of movement Continuous movement Determined by external switch signal input. Incremental movement Determined by external switch signal input. 5.4.1 Continuous movement operation mode (MOD: 02h) It is an operation mode to move continuously while the external switch signal is ON. The operation mode can be terminated by writing STOP (49h) command.
  • Page 120 DA70152-1/0E1 5.5 Origin return control An operation starts by writing the start command. A movement stops by inputting origin signal or encoder Z-phase signal and ends the operation mode. Origin return control uses origin signals or encoder Z-phase signals depending on the operation mode. Input logic (RENV1.ORGL) and input noise filter (RENV1.FLTR) can be set to ORGn terminal to which the origin signal is input.
  • Page 121 DA70152-1/0E1 Input noise filter (EAn, EBn, EZn) <RENV2.EINF(18)> [RENV2] (R/W) 0: Recognizes signals with pulse width of 0.1 μs or wider. 1: Recognizes signals with pulse width of 0.15 μs or wider. - - - - - n - - Set a specified number of encoder Z-phase count <RENV2 EZD(27 to 24)>...
  • Page 122 DA70152-1/0E1 1. Constant speed operation at FL speed in negative direction. 2. Operation stops when the origin signal turns from OFF to ON. 1. Constant speed operation at FH speed in negative direction. 2. Operation stops when origin signal turns from OFF to ON. 1.
  • Page 123 DA70152-1/0E1 5.5.1 Origin return 0 operation mode (RENV2.ORM = 0) An operation mode to perform origin return controls without using encoder Z- phase signal. △: An example operation in the operation mode of positive direction origin return (RMD.MOD = 10h) is shown as follows: Timing to output ON signal from ERCn terminal when “RENV1.EROR = 1”...
  • Page 124 DA70152-1/0E1 5.5.1.3 STAUD(53h) command, Deceleration stops (RENV1.ELM=1) When the operation is completed, the origin position has already been passed. However the counter value will be reliable. When “RENV1.EROR = 1” is set, ON can be output from ERCn terminal at the completion of operation. When “RENV1.EROE = 1”...
  • Page 125 DA70152-1/0E1 5.5.2 Origin return 1 operation mode (RENV2.ORM = 1) An operation mode to perform origin return controls with encoder Z- phase signal. An example operation of two times EZ count (RENV2.EZD = 0001b) in the operation mode of positive direction origin return (RMD.MOD = 10h) is shown as follows: △: Timing to output ON signal from ERCn terminal when “RENV1.EROR = 1”...
  • Page 126 DA70152-1/0E1 5.5.2.2 STAUD(53h) command, Immediate stop (RENV1.ELM=0) When “RENV1.EROR = 1” is set, ON can be output from ERCn terminal at the completion of operation. The operation is completed when EZ count stops. When “RENV1.EROE = 1” is set, ON can be output from ERCn terminal at abnormal stop. When “RENV3.CU1R = 1”...
  • Page 127 DA70152-1/0E1 5.5.2.4 STAUD(53h) command, Deceleration stop(RENV1.ELM = 1), Deceleration (RENV1.SDM = 0), No SD latch(RENV1.SDLT = 0) When “RENV1.EROR = 1” is set, ON can be output from ERCn terminal at the completion of operation. The operation is completed when EZ count stops. When “RENV1.EROE = 1”...
  • Page 128 DA70152-1/0E1 5.6 Linear interpolation control Linear interpolation operation is performed on multiple axes in synchronization with the interpolation axis that has the largest feeding amount. The linear interpolation circuit performs an interpolation between the dummy axis on each axis and its own-axis. Set the interpolation axis data with the largest feeding amount on all dummy axes and perform linear interpolations on all axes indirectly.
  • Page 129 DA70152-1/0E1 Set PRMV register absolute value of the axis whose feeding amount is the largest in the PRIP register of each axis. 5. Set the values of the speed control registers (PRFL, PRFH, PRUR, PRDR, PRMG, PRDP, PRUS, and PRDS) of the axes with the largest feeding amount, to each axis.
  • Page 130 DA70152-1/0E1 [Operation example] X axis output pulse (9) (10) Y axis output pulse 1000pps Z axis output pulse If the Y-axis is 1 (1000 pps), a linear interpolation operation is performed at the speed of 1/2 (500 pps) on X-axis and 1/5 (200 pps) on Z-axis.
  • Page 131 DA70152-1/0E1 5.6.2 Incremental movement operation mode (MOD: 63h) An operation mode to perform an incremental movement with the ratio of the feeding amount set to the interpolation axis. The setting procedure, etc. is the same as the operation mode of continuous movement (MOD: 62h). - 125 -...
  • Page 132 DA70152-1/0E1 6. Speed controls 6.1 Speed pattern list Speed pattern Continuous movement operation mode Incremental movement operation mode FL constant speed start 1) Write STAFL (50h) command. 1) Write STAFL (50h) command. 2) Stop by writing STOP (49h) command or 2) Stop feeding by RPLS = “0”...
  • Page 133 DA70152-1/0E1 6.2 Speed pattern settings Speed setting is specified by using registers shown in the table below. If the next setting value is the same as the current value, there is no need to write again. Name Description Length Setting range Feeding ‘(Target position) amount -2,147,483,648 +2,147,483,647...
  • Page 134 DA70152-1/0E1 6.2.1 Speed control register calculation 6.2.1.1 RFL(PRFL): FL speed setting register Sets the operation speed of FL constant speed start or sets the speed step to calculate the starting or stopping speed in high speed start 1 and 2. FL speed is the calculated value with RMG register.
  • Page 135 DA70152-1/0E1 6.2.1.4 RDR(PRDR): Deceleration rate setting register Sets the deceleration characteristics of high-speed start 2. To select “RMD.MSDP = 0” (auto setting) for the slow-down point, set it the same as RUR register or set it to “0”. When “RDR = 0” is set, the deceleration rate is shared with the RUR register. Calculate the relationship between deceleration time and RDR register using the following formula.
  • Page 136 DA70152-1/0E1 6.2.1.6 RDP(PRDP): Slow-down point setting register Sets slow-down point (deceleration start position). The meaning(=role) of RDP register differs depending on the slow-down point setting method (RMD.MSDP). <Automatic slow-down point setting (RMD.MSDP =0) > Sets the offset of automatic slow-down point setting. When the offset is a positive number, deceleration starts earlier, and it stops after operating at FL speed following completion of deceleration.
  • Page 137 DA70152-1/0E1 6.2.1.7 RUS(PRUS): Acceleration S-curve section setting register Sets S-curve acceleration section in S-curve acceleration/deceleration operation. The range of S-curve acceleration section S is the calculated value with RMG register. The relationship between S and RUS register is calculated by the following formula. ( RMG+1 ) ×16384 Reference clock frequency [Hz] ( RMG+1 ) ×16384...
  • Page 138 DA70152-1/0E1 6.2.2 Speed pattern setting example The following is an example; Reference clock frequency = 19.6608 MHz, FL speed = 10 pps, FH speed = 100 kpps, Acceleration/deceleration time = 300 ms, Linear acceleration/deceleration. 1. FH speed is 100 kpps; set the magnification of 10 times, so that the actual speed range is 100 kpps or more. RMG = 119 (0077h) 2.
  • Page 139 DA70152-1/0E1 <Example of speed pattern when RUR = 294> 100kpps 100 kpps ( FH速度) (FH speed) 10 pps 10pps (FL speed) ( FL速度) 300. 06m s 300. 06m s - 133 -...
  • Page 140 DA70152-1/0E1 6.3 Manual FH correction calculation When accelerating/decelerating in incremental movement operation mode, the speed pattern may become a triangle drive. If the FH speed is too high against the feeding amount, or if the feeding amount is too small against the FH speed, a triangle drive may occur.
  • Page 141 DA70152-1/0E1 6.3.1 Linear acceleration/deceleration speed ( RFH ) × ( RUR + RDR + 2 ) FH speed when “RMD.MSMD = 0” (linear acceleration/deceleration) is set, will be calculated by the following formula. − RFL RMV ≦ ( RMG + 1 ) × 16384 Condition: When ( RMG + 1 ) ×...
  • Page 142 DA70152-1/0E1 6.3.3.2 RUS<RDS 1. When the linear acceleration/deceleration section can be shorter: ( RFH + RFL ) × {( RFH − RFL ) × ( RUR + RDR + 2 ) + 2 × RUS × ( RUR + 1 ) + 2 × RDS × ( RDR + 1 )} Condition: RMV ≦...
  • Page 143 DA70152-1/0E1 6.3.3.3 When RUS>RDS 1. When the linear acceleration/deceleration section can be shorter: ( RFH + RFL ) × {( RFH − RFL ) × ( RUR + RDR + 2 ) + 2 × RUS × ( RUR + 1 ) + 2 × RDS × ( RDR + 1 )} RMV ≦...
  • Page 144 DA70152-1/0E1 6.4 Target speed override In the operation mode of command control continuous movement (RMD.MOD = 00h, 08h) and positioning control incremental movement (RMD.MOD = 41h), the target speed can be overridden by rewriting RFH register during operation. In the command control operation mode, the speed pattern can also be changed by rewriting RUR, RDR, RUS, and RDS registers during operation.
  • Page 145 DA70152-1/0E1 Example of speed pattern change due to the speed change during S-curve acceleration/deceleration Rewrite RFH register during acceleration: If the changed speed is less than the current speed, it decelerates with s-curve to that speed. Rewrite RFH register during acceleration: If the changed speed is equal to or higher than the current speed and equal to or lower than the original target speed, it will accelerate without changing S-curve characteristic.
  • Page 146 DA70152-1/0E1 7. Functions 7.1 Reset After turning ON the power, make sure to reset the LSI at least once before beginning to use it. To reset the LSI, input at least 8 cycles or more of reference clock signal while “RST = L level”. The status after reset is configured as follows.
  • Page 147 DA70152-1/0E1 7.2 Target position override Target position override can be performed during operation mode of incremental movement with positioning control (RMD.MOD = 41h). Do not override target positions in other operation modes. There are two ways to override target positions. 7.2.1 Target position override 1 (RMV register) Target position can be overridden by rewriting RMV register value during operation.
  • Page 148 DA70152-1/0E1 Acceleration or deceleration operation can be performed only in high-speed start 1 and 2. You can override the target position as often as possible, but please consider the restrictions carefully. In the case of setting “RMD.MADJ = 0” (avoiding triangular drive), FH speed is corrected in relation to the initial target position.
  • Page 149 DA70152-1/0E1 7.2.2 Target position override 2 (PCSn) By setting “RENV1.PCSM = 1” and “RMD.MPCS = 1”, the operation will start like continuous movement operation mode. If a pulse count start signal is input, a positioning control starts for the feeding amount set in RMV register. Instead of inputting pulse count start signals, writing STAON command (28h) can start positioning control.
  • Page 150 DA70152-1/0E1 7.3 Output pulse control 7.3.1 Output pulse mode (OUTn, DIRn) For command pulse output modes, there are 4 types of common command pulse modes, 2 types of 2-pulse modes, and 2 types of 90-degree phase difference mode. Command pulse output modes are selected by RENV1.PMD bit. Common pulse mode: Outputs the command pulses from OUTn terminal, and outputs the direction identification signal from DIRn terminal.
  • Page 151 DA70152-1/0E1 7.3.2 Output pulse width control and operation complete timing Change the output pulse width in accordance with the output pulse cycle of command pulses. ON width of output pulse is 50% duty ratio. When RMG register setting is an even number, an error occurs in the duty ratio, so that ON-time becomes shorter than OFF- time.
  • Page 152 DA70152-1/0E1 7.4 Mechanical input control In addition to the end limit switches (PELn, MELn), the origin switch (ORGn), the slow-down switch (SDn), which are assembled in a machine like a slider in the figure below, Z-phase output (EZn) of the rotary encoder is used as an external input trigger in various operations.
  • Page 153 DA70152-1/0E1 Input logic (PELn, MELn) <ELLn input terminal> L: Positive logic H: Negative logic [RENV1] (R/W) Stop method by input (PELn, MELn) <RENV1.ELM(3)> 0: Immediate stop - - - - n - - - 1: Decelerate and stop [RENV1] (R/W) Input noise filter (PELn, MELn, SDn, ORGn, ALMn, INPn, CEMG) <RENV1.FLTR(26)>...
  • Page 154 DA70152-1/0E1 7.4.2 Slow-down signal (SDn) In case “PRMD.MSDE = 1” is set, operation will: 1) decelerate, 2) latch and decelerate, 3) decelerate and stop, or 4) latch and perform a deceleration stop when slow-down signal turns ON during an operation. 1) Deceleration <RENV1.SDM = 0, RENV1.SDLT = 0>...
  • Page 155 DA70152-1/0E1 3) Deceleration stop <RENV1.SDM =1, RENV1.SDLT = 0> - While operating at constant speed pattern, a motor will stop immediately if slow-down signal turns ON. - While in high-speed start pattern, a motor will decelerate to FL speed and then stop when slow-down signal turns ON. If slow-down signal turns OFF during deceleration, it will accelerate to FH speed.
  • Page 156 DA70152-1/0E1 The input logic of SDn terminal can be changed. If “RENV1.SDLT = 1” (latched input) is selected for slow-down signal input, the latch will be reset when SDn terminal is OFF at the following start. The latch is also reset when “RENV1.SDLT = 0” (latch input release) is set again. The minimum pulse width of slow-down signal is for 2 cycles of CLK signal (0.1 μs) when input noise filter of SDn terminal is OFF.
  • Page 157 DA70152-1/0E1 [REST] (R/W) Obtain the error interrupt factor <REST.ESSD(5)> 1: Stopped by slow-down signal ON. - - n - - - - - [RENV1] (R/W) Input noise filter (PELn, MELn, SDn, ORGn, ALMn, INPn, CEMG) <RENV1.FLTR(26)> 0: Recognizes pulse width of 0.1 μs or wider. - - - - - n - - 1: Recognizes pulse width equals to or wider than the value set by RENV1.FTM bit [RENV1]...
  • Page 158 DA70152-1/0E1 [PRMD] (R/W) Operation mode <PRMD.MOD(6 to 0)> 0010000b (10h): Positive direction origin return control mode by origin return control 0 n n n n n n n 0011000b (18h): Negative direction origin return control mode by origin return control [RENV2] (R/W) Encoder Z-phase signal setting...
  • Page 159 DA70152-1/0E1 7.5 Servo motor interface Various controls can be performed by connecting with the in-position output (INP), deviation counter clear input (ERC) and alarm output (ALM) of servo motor drivers. 7.5.1 In-position signal (INPn) The pulse-train input type servo drivers have deviation counters to count the difference between command pulse inputs and feedback pulse inputs.
  • Page 160 DA70152-1/0E1 7.5.2 Deviation counter clear signal (ERCn) A servo motor does not stop until the deviation counter in a servo driver reaches “0”, even after command pulses have stopped being output. Therefore, even if the output of the command pulse is stopped, the immediate stop may not be performed in some cases.
  • Page 161 DA70152-1/0E1 <RENV1.EROE(10)> [RENV1] (R/W) Output function at abnormal stop (ERCn) The deviation counter clear signal can be output when stopped by turning ON PELn, MELn, ALMn, and CEMG terminals. Also, when stopped by writing CMEMG (05h) command. - - - - - n - - 0: Deviation counter clear signal ON is not output.
  • Page 162 DA70152-1/0E1 7.5.3 Alarm signals (ALMn) Inputs alarm signal to ALMn terminal. When alarm signal turns ON while in operation, the motor will stop immediately or decelerate and stop. For constant speed pattern, only “stop immediately” is available. In high speed patter, the choice can be made to stop immediately or to decelerate and stop. If an alarm signal is ON, THE LSIA will not output any pulses even when a start command is written.
  • Page 163 DA70152-1/0E1 7.6 Simultaneous start 7.6.1 Simultaneous start signal (CSTA) When connecting CSTA terminal, multi axes can be started simultaneously. Writing CMSTA (06h) command enables to output a negative logic one-shot pulse from CSTA terminal. When “CSTA = L level”, multi axes that have waited for a simultaneous start input, can be started simultaneously. When “CSTA = L level”, an event interrupt can be generated.
  • Page 164 DA70152-1/0E1 [PRMD] (R/W) Waiting for input <PRMD.MSY(19, 18)> 01b: If “RENV1.PCSM = 0”, it starts with “CSTA = L level” or with SPSTA (2Ah) command. - - - - n n - - If “RENV1.PCSM = 1”, it starts with PCSn terminal ON or with SPSTA (2Ah) command. <RENV1.STAM(18)>...
  • Page 165 DA70152-1/0E1 7.6.2 Own-axis start signal (PCSn) When “PRMD.MSY = 01b” and “RENV1.PCSM = 1” are selected, only the own-axis can be started by inputting the own-axis start signal to PCSn terminal. If “RENV1.PCSM = 1” is selected, it will not start with simultaneous start signal input to CSTA terminal. You can start by writing SPSTA (2Ah) command.
  • Page 166 DA70152-1/0E1 7.7 Simultaneous deceleration 7.7.1 Simultaneous slow-down signal (CSD) When CSD terminal is connected, multiple axes can be simultaneously decelerated by linear interpolation operation. “CSD = L level” can be output during FL constant speed or deceleration. (PRMD.MCDO = 1) When “CSD = L level”...
  • Page 167 DA70152-1/0E1 7.8 Simultaneous stop 7.8.1 Simultaneous stop signal (CSTP) Multiple axes can be stopped at the same time if the CSTP terminals are connected. “CSTP = L level” can be output when writing CMSTP (07h) command or occurring abnormal stops. (PRMD.MSPO = 1) When “CSTP = L level”, stop immediately if “RENV1.STPM = 0”...
  • Page 168 DA70152-1/0E1 <PRMD.MSPE(24)> [PRMD] (R/W) Input function (CSTP) Stops own-axis with abnormal stop of other axes. 0 0 - - - - - n 0: General-purpose input. CSTP terminal status can be obtained by RSTS.SSTP bit. 1: Input simultaneous stop signal to CSTP terminal to decelerate & stop or stop immediately. <RENV1.STPM(19)>...
  • Page 169 DA70152-1/0E1 7.9 Emergency stop 7.9.1 Emergency stop signal (CEMG) When CMEMG (05h) command is written or CEMG = L level, all the axes will stop emergently. At an abnormal stop, error interrupt (REST.ESEM) will occur. When error interrupt (REST.ESEM) on all axes, including stopped or unused, are cleared, it becomes “INT = H level”. While CEMG = L level, no axis will operate.
  • Page 170 DA70152-1/0E1 7.10 Counters 7.10.1 Counter type and input specification The LSI has three built-in counters; one in-position counter (RPLS) and two counters (RCUN 1, RCUN 2) per axis. The positioning counter copies the absolute value of RMV register at start and counts down at every command pulse output. While “RMD.MPCS = 1”...
  • Page 171 DA70152-1/0E1 <RENV2.EINF(18)> [RENV2] (R/W) Input noise filter(EAn, EBn, EZn) Selects the noise filter of EAn, EBn, EZn terminals. - - - - - n - - 0: Recognizes signals with a pulse width of 0.1 μs or wider. 1: Recognizes signals with a pulse width of 0.15μs or wider. <RENV2.EIM(17, 16)>...
  • Page 172 DA70152-1/0E1 3) When using input of 90-degree phase difference mode of 4 multiplication. Counter 4) When using 2-pulse input (counted on the rising edge from L to H). Counter 7.10.2 Latch and clear (LTCn) 7.10.2.1 Latch 1 and 2 RLTC1 register can latch, or latch & clear the Counter 1 in three ways. RLTC2 register can latch, or latch & clear the Counter 2 in three ways.
  • Page 173 DA70152-1/0E1 <RENV1.LTCL(23)> [RENV1] (R/W) Input specification (LTCn) 0: Falling edge. n - - - - - - - 1: Rising edge. [RSTS] LTCn terminal status <RSTS.SLTC(13)> 1: When “RENV1.LTCL = 0”, “LTCn = L level” - - n - - - - - When “RENV1.LTCL = 1”, “LTCn = H level”...
  • Page 174 DA70152-1/0E1 Obtains the event interrupt factor <RIST.ISOL(9)> [RIST] (R/W) 1: Origin position signal turns ON. - - - - - - n - [Command] Counter 1 clear command <CUN1R> Clear counter 1 (RCUN1). Counter 2 clear command <CUN2R> [Command] Clear counter 2 (RCUN2). Counter 1 &...
  • Page 175 DA70152-1/0E1 In operation example 1: Selects a value other than “invalid” (RENV4.L3T ≠ 000b) as the trigger signal of RLTC3 register and selects “RENV4.L3MD = 0” (latched only with the first trigger signal) as the latch operation specification. <Operation Example 1> 1.
  • Page 176 DA70152-1/0E1 Operation example 2: Selecting a value other than “invalid” (RENV4.L3T ≠ 000b) as the trigger signal of RLTC3 register and selecting “RENV4.L3MD = 1” (latched with every trigger signal) as latch operation specification. <Operation Example 2> 1. Before writing LTC3E (3Ch) command, the trigger signal is ON but will not latch. RSTS.SL3C bit and RSTS.SL3F bit also do not change.
  • Page 177 DA70152-1/0E1 Counter to latch to RLTC3 register <RENV4.L3DT(4)> [RENV4] (R/W) 0: Select Counter 1 (RCUN1). - - - n - - - - 1: Select Counter 2 (RCUN2). Input terminal for the trigger signal latched to RLTC3 register <RENV4.L3T(2 to 0)> [RENV4] (R/W) 000: Invalid...
  • Page 178 DA70152-1/0E1 Input terminal for the trigger signal latched to RLTC4 register [RENV4] (R/W) <RENV4.L4T(10 to 8)> 000: Invalid 00: LTCn terminal 010: ORGn terminal 011: EZn terminal - - - - - n n n 100: P4n terminal 101: P5n terminal 110: P6n terminal 111: P7n terminal Input specification for the trigger signal latched to RLTC4 register...
  • Page 179 DA70152-1/0E1 7.10.3 Counting stops and input stops Counters 1 and 2 have counting stop (RENV3.CU1H, RENV3.CU2H) and input stop (PRMD.MCCE, RENV2.EOFF). Counter 1 (RCUN1) and Counter 2 (RCUN2) can be stopped separately when counting is stopped. When counting input is stopped, the counter that selects the corresponding input will stop. In the operation mode of timer (RMD.MOD = 47h), the counter that has selected the command position to count will stop.
  • Page 180 DA70152-1/0E1 7.11 Comparators 7.11.1 Comparator types and functions The LSI has four built-in 32-bit comparators per axis. Comparator 1: Compares the setting value in the Comparator 1 (RCMP1) with Counter 1 (RCUN1). Comparator 2: Compares the setting value in the Comparator 2 (RCMP2) with Counter 2 (RCUN2). Comparator 3 and 4 are used only for software limit functions.
  • Page 181 DA70152-1/0E1 Obtains Event interrupt factor <RIST.ISC2(7)> [RIST] (R/W) 1: Condition of Comparator 2 is met. n - - - - - - - Obtains Comparator 1 status <MSTS.SCP1(8)> [MSTS] 0: Condition of Comparator 1 is not met. - - - - - - - n 1: Condition of Comparator 1 is met.
  • Page 182 DA70152-1/0E1 7.11.2 Ring count function COUNTER 1 and COUNTER 2 can be set for Ring count function to control a rotating table. When using the Ring count function, set positive numbers to RCMP1 register and RCMP2 register. When “RENV3.C1RM = 1” (Ring counter) is set in COUNTER 1 (RCUN1), the LSI can perform the following operations: - Count value will be “0”...
  • Page 183 DA70152-1/0E1 7.11.3 Software limit function In addition to hardware limit switch controls by positive or negative direction signal, software limit controls can be used. Comparator 3 comparison value (RCMP 3) is the positive direction software limit value (PSL). Comparator 4 comparison value (RCMP 4) is the negative direction software limit value (MSL). Counters for software limit managements can be selected (RENV3.SLCU) from COUNTER 1 (RCUN1) and COUNTER 2 (RCUN2).
  • Page 184 DA70152-1/0E1 <RENV3.SLM(23, 22)> [RENV3] (R/W) Software limit function 00b: Operation does not stop at software limit positions, and no interrupt is generated. n n - - - - - - 01b: Operation does not stop at software limit positions, and an event interrupt is generated. 10b: Operation stops immediately at software limit positions, and an error interrupt is generated.
  • Page 185 DA70152-1/0E1 7.12 Synchronous starting There are two types of start that synchronize with the movements of other axes. 7.12.1 Starts by stopping the target axis When “PRMD.MSY = 11b” is selected for start timing and then start, RSTS.CND becomes 0100b. After that, when any target axis (RMD.MAX) starts and the all target axes stop, the own-axis will start.
  • Page 186 DA70152-1/0E1 7.12.2 Start by internal synchronous signal When “PRMD.MSY = 10b” is selected for start timing and then start, RSTS.CND becomes “0011b”. After that, when an internal synchronous signal is output from the target axis (RENV3.SYI), the own-axis starts. There are 6 types of output condition (RENV3.SYO) for the internal synchronous signal. Event interrupts (RIST.ISUS, ISUE, ISDS, ISDE, ISC1, and ISC2) related to output conditions can be generated.
  • Page 187 DA70152-1/0E1 The following Setting example 2 shows to use a fulfillment of comparator condition as the internal synchronization signal. [Setting Example 2] After setting step 1) to 5) below, write start commands to both X- and Y-axes so that Y-axis will start. When the counter 1 (RCUN1) of Y-axis matches “1000”...
  • Page 188 DA70152-1/0E1 7.13 Interrupt (INT) function This LSI can output an interrupt requesting signal (INT = L level) from INT terminal. Interrupt signal is output triggered by 11 types of errors, 20 types of events, and 1 type of change from operating to stop; totaling 32 types.
  • Page 189 DA70152-1/0E1 Outputs of interrupt requesting signals can be stopped with “RENV1.INTM = 1”. When an interrupt request signal output is stopped, it will not change to “INT = L level” when an interrupt occurs. Main-status and interrupt factor register can change. When “RENV1.INTM = 0”...
  • Page 190 DA70152-1/0E1 7.13.1 Error interrupt factors REST Error interrupt factors <Interrupt factor occurs when the corresponding bit is “1”.> Position Name Stopped by positive direction end limit signal turned ON. ESPL Stopped by negative direction end limit signal turned ON. ESML Stopped by alarm signal ON, or alarm signal turned ON while stopping.
  • Page 191 DA70152-1/0E1 7.13.2 Event interrupt factors RIRQ RIST Event interrupt factors <When an interrupt factor is set and is occurred, the corresponding bit becomes “1”.> Position Name Position Name Stopped normally. IREN ISEN Pre-register changed to write enabled. IRNM ISNM Acceleration started. IRUS ISUS Acceleration ended.
  • Page 192 ID codes can be read only when IDMON (03h) command and RRMG (D5h) command are used continuously. If RRMG (D5h) command is used other than the above procedure, the ID code part will be “0”. The ID codes are as shown in the table below. ID code PCL6115 03E0h PCL6125 03F0h...
  • Page 193 DA70152-1/0E1 8. Electrical Characteristics 8.1 Absolute maximum ratings Item Name Rating Unit Remark − 0.3 to + 4.0 Power supply voltage − 0.3 to + 7.0 Input voltage − 30 to + 30 Output current − 65 to + 150 Storage temperature Tstg °C...
  • Page 194 DA70152-1/0E1 8.3 DC characteristics 8.3.1 PCL6115 Item Name Condition Min. Max. Unit Consumption current CLK = 30 MHz, 15 Mpps per axis, No load Input capacity A0 to A2, D0 to D15, CLK L level input current = GND) Input terminals other than the above (Note)
  • Page 195 DA70152-1/0E1 8.3.2 PCL6125 Item Name Condition Min. Max. Unit CLK = 30 MHz, 2 axes at 15 Mpps, no Consumption current load Input capacity A0 to A3, D0 to D15, CLK L level input current = GND) Input terminals other than the above -125 (Note) H level input current...
  • Page 196 DA70152-1/0E1 8.3.3 PCL6145 Item Name Condition Min. Max. Unit CLK = 30 MHz, 4 axes at 15 Mpps, no Consumption current load Input capacity −1 A0 to A4, D0 to D15, CLK L level input current = GND) Input terminals other than the above −125 (Note) H level input current...
  • Page 197 DA70152-1/0E1 8.4 AC characteristics 8.4.1 Reference Clock 8.4.1.1 PCL6115 Item Name Min. Max. Unit Reference clock frequency Reference clock cycle Reference clock H level width Reference clock L level width 8.4.1.2 PCL6125 Item Name Min. Max. Unit Reference clock frequency...
  • Page 198 DA70152-1/0E1 8.4.2 16-bit interface-1 (68000, etc.) Setting: IF1 terminal = L level, IF0 terminal = L level. <Read cycle> A4-A1 LS(A0) R/W(WR) SLAKR SHAKR ACK(WRQ) DAKLR D15-D0 <Write cycle> A4-A1 LS(A0) R/W(WR) SLAKW SHAKW ACK(WRQ) AKDH D15-D0 - 192 -...
  • Page 199 DA70152-1/0E1 8.4.2.1 PCL6115 Item Name Condition Min. Max. Unit for LS ↑ Address setup time for LS ↑ Address hold time for LS ↓ CS setup time for LS ↑ CS hold time for LS ↓ R/W setup time for LS ↑...
  • Page 200 DA70152-1/0E1 8.4.2.3 PCL6145 Item Name Condition Min. Max. Unit for LS ↓ Address setup time for LS ↑ Address hold time for LS ↓ CS setup time for LS ↑ CS hold time for LS ↓ R/W setup time for LS ↑ R/W hold time = 40pF 4･T...
  • Page 201 DA70152-1/0E1 8.4.3 16-bit interface-2 (H8, etc.) Setting: IF1 terminal = L level, IF0 terminal = H level <Read cycle> A4-A1 RWCS CSWT WAIT RDLD WTHD RDHD D15-D0 <Write cycle> A4-A1 RWCS CSWT WAIT D15-D0 - 195 -...
  • Page 202 DA70152-1/0E1 8.4.3.1 PCL6115 Item Name Condition Min. Max. Unit for RD ↓ Address setup time for WR ↓ Address setup time for RD, WR ↑ Address hold time CS setup time for RD↓ for WR ↓ CS setup time for RD, WR ↑...
  • Page 203 DA70152-1/0E1 8.4.3.3 PCL6145 Item Name Condition Min. Max. Unit for RD ↓ Address setup time for WR ↓ Address setup time for RD, WR ↑ Address hold time CS setup time for RD↓ for WR ↓ CS setup time for RD, WR ↑ CS hold time RWCS WRQ ON delay time...
  • Page 204 DA70152-1/0E1 8.4.4 16-bit interface-3 (8086, etc.) Setting: IF1 terminal = H level, IF0 terminal = L level <Read cycle> A4-A1 RWCS CSWT WAIT RDLD WTHD RDHD D15-D0 <Write cycle> A4-A1 RWCS CSWT WAIT D15-D0 - 198 -...
  • Page 205 DA70152-1/0E1 8.4.4.1 PCL6115 Item Name Condition Min. Max. Unit for RD ↓ Address setup time for WR ↓ Address setup time for RD, WR ↑ Address hold time CS setup time for RD↓ for WR ↓ CS setup time for RD, WR ↑...
  • Page 206 DA70152-1/0E1 8.4.4.3 PCL6145 Item Name Condition Min. Max. Unit for RD ↓ Address setup time for WR ↓ Address setup time for RD, WR ↑ Address hold time CS setup time for RD↓ for WR ↓ CS setup time for RD, WR ↑ CS hold time RWCS for CS ↓...
  • Page 207 DA70152-1/0E1 8.4.5 8-bit interface (Z80, etc.) Setting: IF1 terminal = H level, IF0 terminal = H level <Read cycle> A4-A1 RWCS CSWT WAIT RDLD WTHD RDHD D7-D0 <Write cycle> A4-A1 RWCS CSWT WAIT D7-D0 - 201 -...
  • Page 208 DA70152-1/0E1 8.4.5.1 PCL6115 Item Name Condition Min. Max. Unit for RD ↓ Address setup time for WR ↓ Address setup time for RD, WR ↑ Address hold time CS setup time for RD↓ for WR ↓ CS setup time for RD, WR ↑...
  • Page 209 DA70152-1/0E1 8.4.5.3 PCL6145 Item Name Condition Min. Max. Unit for RD ↓ Address setup time for WR ↓ Address setup time for RD, WR ↑ Address hold time for RD ↓ CS setup time for WR ↓ CS setup time for RD, WR ↑...
  • Page 210 DA70152-1/0E1 8.4.6 Serial interface Setting: RD = L level, WR = L level <Read cycle> SHSL ADDR MOSI LSB IN CLQV CLQV SHQZ MISO LSB OUT Hi-Z Hi-Z <Write cycle> SHSL SLCH CHSH DVCH CHDX MOSI MISO Hi-Z - 204 -...
  • Page 211 DA70152-1/0E1 8.4.6.1 PCL6115 Item Name Condition Unit Serial clock frequency /1.5 Serial clock cycle Serial clock H time Serial clock L time SS signal active setup 10+T SLCH SS signal deselect time 4･T SHSL SS signal active hold time CHSH...
  • Page 212 DA70152-1/0E1 8.4.6.3 PCL6145 Item Name Condition Unit Serial clock frequency /1.5 Serial clock cycle Serial clock H time Serial clock L time SS signal active setup 10+T SLCH SS signal deselect time 4･T SHSL SS signal active hold time CHSH Data setup time DVCH Data hold time...
  • Page 213 DA70152-1/0E1 8.5 Operation timing (common for all axes) Input signal width is a pulse width that can be recognized; output signal width is a pulse width to be output. Min/Max is the time required to be processed. Item Name Condition Min.
  • Page 214 DA70152-1/0E1 8.5.1 Encoder signal input (2-pulse mode) 8.5.2 Encoder signal input (90-degree phase difference mode) 8.5.3 Manual pulser signal input (2-pulse mode) 8.5.4 Manual pulser signal input (90-degree phase difference mode) - 208 -...
  • Page 215 DA70152-1/0E1 8.5.5 To start an operation by writing a start command: Writing a start command CMDBSY CMDPLS 1st output pulse 8.5.6 To start an operation by simultaneous start signal input: CSTA STABSY STAPLS 1st output pulse 8.5.7 To start decelerating by slow-down FL speed change or writing deceleration stop command: CMDFDW 8.5.8 To start decelerating by slow-down signal input:...
  • Page 216 DA70152-1/0E1 8.5.9 Immediate stop command writing (continuous movement operation mode): Stop interrupt MSTS. SSCM MSTS. SRUN MSTS. SENI MSTS. SEND RSTS. 0000 CND3-0 8.5.10 Normal stop (incremental movement operation mode): Event interrupt MSTS. SSCM MSTS. SRUN MSTS. SEND MSTS. SINT RIST.
  • Page 217 DA70152-1/0E1 8.5.11 Abnormal stop (incremental movement operation mode): Error interrupt MSTS. SSCM MSTS. SRUN MSTS. SEND MSTS. SERR REST Error cause bit changed RSTS. 0000 CND3-0 - 211 -...
  • Page 218 DA70152-1/0E1 9. Handling Precautions 9.1 Design precautions Regarding operating voltage, current, temperature, I/O voltage / current etc., please use this product within the rated range. If used outside the rating range, even if it operates normally in the short term, there is a possibility of increasing the failure rate.
  • Page 219 DA70152-1/0E1 9.4 Precautions for installation Plastic packages absorb moisture easily. Even if they are stored indoors, they will absorb moisture as time passes. If LSI that has absorbed moisture is put into a solder reflow furnace, cracks may occur in the resin or adhesion between the resin and the frame may deteriorate.
  • Page 220 DA70152-1/0E1 Revision Revision Date Contents First May 9, 2018 New document Second April 5, 2019 Overall layouts and contents are revised from the first version. - 214 -...
  • Page 221 DA70152-1/0E1 www.pulsemotor.com/group/ Information www.pulsemotor.com/group/support Issued in Apr 2019 Copyright 2019 Nippon Pulse Motor Co., Ltd.

This manual is also suitable for:

Pcl6125Pcl6145

Table of Contents