Sanyo LC78625E Manual

Compact disc player dsp

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Ordering number : EN5502

Overview

The LC78625E is a CMOS LSI that implements the signal

processing and servo control required by compact disc

players, laser discs, CD-V, CD-I and related products. The

LC78625E provides several types of signal processing,

including demodulation of the optical pickup EFM signal,

de-interleaving, error detection and correction, and digital

filters that can help reduce the cost of CD player units. It

also processes a rich set of servo system commands sent

from the control microprocessor. It also incorporates an

EFM-PLL circuit and a one-bit D/A converter.

This LSI is an improved version of the LC78620E. In

addition to supporting low-voltage operation, on/off

control of the de-emphasis function and use of the

bilingual function have been enabled in certain additional

modes.

Functions

• The LC78625E takes an HF signal as input, digitizes

(slices) that signal at a precise level, converts that signal

to an EFM signal, and generates a PLL clock with an

average frequency of 4.3218 MHz by comparing the

phases of that signal and an internal VCO.

• A precise reference clock and the necessary internal

timings are generated using an external 16.9344 MHz

crystal oscillator.

• Disc motor speed control using a frame phase difference

signal generated from the playback clock and the

reference clock

• Frame synchronization signal detection, protection, and

interpolation to assure stable data readout

• EFM signal demodulation and conversion to 8-bit

symbol data

• Subcode data separation from the EFM demodulated

signal and output of that data to an external

microprocessor

• Subcode Q signal output (LSB first) to a microprocessor

over the serial interface after performing a CRC error

check

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Compact Disc Player DSP

• Demodulated EFM signal buffering in internal RAM to

handle up to ±4 frames of disc rotational jitter

• Demodulated EFM signal reordering in the prescribed

order for data unscrambling and de-interleaving

• Error detection, correction, and flag processing (error

correction scheme: dual C1 plus dual C2 correction)

• The LC78625E sets the C2 flags based on the C1 flags

and a C2 check, and then performs signal interpolation

or muting depending on the C2 flags. The interpolation

circuit uses a quadruple interpolation scheme. The

output value converges to the muting level when four or

more consecutive C2 flags occur.

Package Dimensions

unit: mm

3174-QFP80E

[LC78625E]

CMOS LSI

LC78625E

SANYO: QFP80E

22897HA (OT) No. 5502-1/35

Table of Contents

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Summary of Contents for Sanyo LC78625E

Page 1 C1 plus dual C2 correction) including demodulation of the optical pickup EFM signal, • The LC78625E sets the C2 flags based on the C1 flags de-interleaving, error detection and correction, and digital and a C2 check, and then performs signal interpolation filters that can help reduce the cost of CD player units.
Page 2 LC78625E • Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8-bit serial input) • Built-in digital output circuits. • Arbitrary track counting to support high-speed data access •...
Page 3: Pin Assignment
LC78625E Pin Assignment Specifications Absolute Maximum Ratings at Ta = 25°C, V = 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage – 0.3 to +7.0 Maximum input voltage – 0.3 to V + 0.3 Maximum output voltage – 0.3 to V + 0.3...
Page 4 LC78625E Continued from preceding page. Ratings Parameter Symbol Conditions Unit Command transfer time RWC : Figure 1 1000 Subcode Q read enable time WRQ: Figure 2, with no RWC signal 11.2 Subcode read cycle SFSY : Figure 3 µs Subcode read enable time...
Page 5 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) Note: Measured with the normal-speed playback mode digital attenuator in the Sanyo one-bit D/A converter block reference circuit. Figure 1 Command Input Figure 2 Subcode Q Output Figure 3 Subcode Output No.
Page 6 LC78625E Figure 4 General-Purpose Port Input Timing Figure 5 General-Purpose Port Output Timing No. 5502-6/35...
Page 7 LC78625E One-Bit D/A Converter Output Block Reference Circuit No. 5502-7/35...
Page 8: Pin Functions
LC78625E Pin Functions Pin No. Symbol Function DEFI Defect detection signal (DEF) input (This pin must be connected to 0 V if unused.) Test input. A pull-down resistor is built in. (This pin must be connected to 0 V in normal operation.) External VCO control phase comparator output Internal VCO ground.
Page 9 LC78625E Continued from preceding page. Pin No. Symbol Function ASDACK/P0 • When antishock mode is not used, Bit clock input these pins are used as general- ASDFIN/P1 Left and right channel data input purpose I/O ports (P0 to P3). They The antishock inputs in Sets the built-in de-emphasis filter on or off.
Page 10 2. PLL clock generation circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78625E includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is...
Page 11 LC78625E 3. VCO monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two. 4. Synchronization detection monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree.
Page 12 NOTHING The FOCS, FST, and FZD pins are not required when the LC78625E is used in combination with an LA9230/40 Series LSI. FZD should be connected to 0 V when these pins are not used. The LA9230/40 Series focus start command is identical to the LC78625E FOCUS START #1 command.
Page 13 LC78625E Note:* Values in parentheses are for the FOCUS START #2 command. The only difference is in the FST low period. * An FZD falling edge will not be accepted during the period that FST is low. * After issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not issue the next command during focus start until the focus coil drive S curve has completed.
Page 14 • CLV mode In CLV mode the LC78625E detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM period corresponds to a frequency of 7.35 kHz.
Page 15 LC78625E • Phase control gain switching Code COMMAND RES = L CLV phase comparator divisor: 1/2 CLV phase comparator divisor: 1/4 CLV phase comparator divisor: 1/8 No CLV phase comparator divisor used The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator.
Page 16 TON mode during internal braking Reset TON mode — Issuing the internal brake on command ($C5) sets the LC78625E to internal brake mode. In this mode, the disc deceleration state can be monitored from the WRQ pin when a brake command ($06) is executed.
Page 17 (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78625E detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TE signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL.
Page 18 When the LC78625E is used in combination with an LA9230/40 Series LSI, since the THLD signal is generated by the LA9230/40, the THLD pin (pin 25) will be unused, and should be left open.
Page 19 Track check out Two-byte command reset The LC78625E will count the specified number of tracks when the microprocessor sends an arbitrary binary value in the range 8 to 254 after issuing either a track check in or a track check out command.
Page 20 LC78625E Note:*When the desired track count has been input in binary, the track check operation is started by the fall of RWC. * During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required.
Page 21 (See the items on track counting and internal braking for details.) The LC78625E becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state.
Page 22 (Normal operation uses relative time.) — It is possible to set the LC78625E to ignore values larger than the already recorded value by issuing the PKM mask set command, even in PKM mode. This function is cleared by issuing a PKM mask reset command. (This is used in PK search in a memory track.)
Page 23 Since the attenuation level is set to the muted state (a muting of -∞ is specified by an attenuation coefficient of 00H) after the LC78625E is reset, the attenuation coefficient must be directly set to EEH (using the ATT DATA SET command) to output audio signals.
Page 24 LC78625E ATT DATA Audio output level = 20 log ——————— [dB] 100H For example, the formula below calculates the time required for the attenuation level to increase from 00H to EEH when a 4STEP UP command is executed. Note that the control microprocessor must provide enough of a time margin for this operation to complete before issuing the next attenuation level set command.
Page 25 19. One-bit D/A converter The LC78625E PWM block outputs a single data value in the range –3 to +3 once every 64fs period. To reduce carrier noise, this block adopts an output format in which each data switching block is adjusted so that the PWM output level does not invert.
Page 26 • It is possible to input the signals from the ROMXA (pin 44), C2F (pin 45), LRSY (pin 42), and CK2 (pin 43) pins to an antishock LSI (the Sanyo LC89151) and re-input the signals output by the antishock LSI to the ASDFIN (pin 39), ASLRCK (pin 41), and ASDACK (pin 38) pins.
Page 27 Note that the LC78625E adds a general-purpose I/O port function that shares the ASDACK, ASDFIN, ASDEPC, and ASLRCK pins. Applications that use the LC78625E with antishock mode turned on must set the P0 (ASDACK), P1 (ASDFIN), P2 (ASDEPC), and P3 (ASLRCK) pins to input mode by issuing a port I/O switching command ($DB0x).
Page 28 LC78625E 24. CONT pin; Pin 73: CONT Code COMMAND RES = L CONT Set CONT and CD-ROM XA reset The CONT pin goes high when a CONT SET command is issued. 25. Clock oscillator; Pin 77: XIN, pin 78: XOUT...
Page 29 28. Sound output function for set adjustment during manufacturing; Pin 30: DEMO The DEMO pin can be used when the LC78625E is used in combination with an LA9210M or LA9211M. By setting this pin high, muting can be set to 0 dB, the disc motor can be set to CLV, and a focus start operation can be performed, even without issuing any commands from the control microprocessor.
Page 30 PCK side of the CLV servo circuit. If the ±4 frame buffer capacity is exceeded, the LC78625E forcibly sets the write address to the ±0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period.
Page 31: Command Summary Table
LC78625E Command Summary Table Blank entry: Illegal command, #: Command added since or changed from the LC78620/1E specifications, : Latching commands (mode setting commands), : Commands shared with an ASP (LA9230M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes) (ADJ.
Page 32 LC78625E Continued from preceding page. Old TRACK JMP ATT DATA SET New TRACK JMP Double speed ATT 4STP UP FOCS START #2 Normal speed ATT 4STP DWN Internal BRKE CONT ATT 8STP UP Internal BRK OFF ATT 8STP DWN Internal BRK ON...
Page 33 LC78625E Sample Application Circuit No. 5502-33/35...
Page 34 LC78625E Differences between the LC78625E and the LC78620E LC78625E LC78620E Item Content of change Bilingual processing for antishock input data is now possible in antishock mode. The same bilingual control commands as those used in the LC78620E are used. A bilingual processing function is not...
Page 35 Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

Sanyo LC78625E Manual

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Summary of Contents for Sanyo LC78625E

Page 3: Pin Assignment

Page 8: Pin Functions

Page 31: Command Summary Table

Table of Contents