THine THCV241A Manual

Serdes transmitter with bi-directional transceiver with processor by v-by-one hs
Table of Contents

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THCV241A_Rev.2.11_E
1

General Description

THCV241A is designed to support 1080p60 2Mpixel
uncompressed video data over 15m 100ohm
differential STP or single-end 50ohm Coaxial cable
with 4 in-line connectors between camera and
®
processor by V-by-One
THCV241A supports a MIPI CSI-2. Each CSI-2 data
lane can transmit up to 1.2Gbps/lane. Virtual channel
is supported.
One high-speed V-by-One® HS lane can transmit up
to 1080p60fps. The maximum serial data rate is
4Gbps/lane. 2nd output lane supports HDR large
amount of data or data copy-and-distribution
experience.
THCV241A is capable to control and monitor
camera module from remote ECU via GPIO, UART or
1Mbps 2-wire serial interface.
Several fault and error detection function including
CRC provides hardware functional safety design.
3

Block Diagram

Copyright©2023 THine Electronics, Inc.
THCV241A
SerDes transmitter with bi-directional transceiver
HS.
MIPI CSI-2
Rx 4-lane
RD3p
RD3n
RD1p
RD1n
RCKp
RCKn
RD0p
RD0n
RD2p
RD2n
CKI
Settings
GPIO
Controls
2-wire
serial I/F
2

Features

MIPI CSI-2 with 1,2 or 4-lane input
MIPI D-PHY supports 80Mbps~1.2Gbps
MIPI Virtual channel supported
Video formats: RAW8/10/12/14/16/20,
YUV422/420, RGB888/666/565, JPEG, User-
defined generic 8-bit
®
V-by-One
®
V-by-One
Reference clock input CKI range 10~40MHz
shareable with video source CMOS sensor
Wide range IO voltage from 1.7V to 3.6V
Additional spread spectrum to reduce EMI
2-wire serial interface 1Mbps bridge function
Remote GPIO/UART control and monitoring
Error detection including CRC and notification
QFN40 5x5mm 0.4mm pitch Exp-pad package
THCV241A
OSC
1/68
HS 400Mbps~4Gbps x2lane
HS standard version1.5
V-by-One® HS
Tx 2 lane
TX0N
TX0P
TX1N
TX1P
Sub-Link
TCMN
TCMP
THine Electronics, Inc.
SC: E

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Summary of Contents for THine THCV241A

  • Page 1: General Description

    4 in-line connectors between camera and  Video formats: RAW8/10/12/14/16/20, ® processor by V-by-One YUV422/420, RGB888/666/565, JPEG, User- THCV241A supports a MIPI CSI-2. Each CSI-2 data defined generic 8-bit lane can transmit up to 1.2Gbps/lane. Virtual channel  ® V-by-One HS 400Mbps~4Gbps x2lane is supported.
  • Page 2: Table Of Contents

    2-wire serial interface ..........................32 6.17.1 2-wire serial I/F slave Device ID ....................32 6.17.2 2-wire serial Read/Write access to local Register ................33 6.18 2-wire serial I/F Watch Dog Timer ......................34 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 2/68...
  • Page 3 11.4 2-wire serial Master/Slave AC Specifications ..................65 Package ..............................67 Notices and Requests ..........................68 MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions. THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 3/68...
  • Page 4: Pin Configuration

    RD3N TX0N RD1P 41 EXPGND TX0P RD1N TX1N RCKP TX1P RCKN TEST RD0P TCMN RD0N TCMP RD2P PDN1 RD2N VDDB 1 2 3 4 5 6 7 8 9 10 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 4/68...
  • Page 5: Pin Description

    Exposed Pad Ground : Must be tied to Ground *type symbol MI=MIPI Input, CO=CML Output CB=CML Bi-directional input/output B=1.8~3.3V CMOS Bi-directional input/output, I=1.8~3.3v CMOS Input, O=1.8~3.3v CMOS Output P=Pow er, G=Ground THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 5/68...
  • Page 6: Functional Description

    Functional Description Functional Overview THCV241A can receive MIPI CSI-2 video and transmit it to over 15m length. With High Speed CML SerDes, high reliability and robustness encoding scheme and CDR (Clock and Data Recovery) architecture, the THCV241A enables to transmit RAW/YUV/RGB/JPEG/Generic8bit data through Main-Link by single 100ohm differential pair or 50ohm Coax cable with minimal external components.
  • Page 7: Mipi Input Setting

    MIPI Data Lane Enable 0x102D R_RX_DATALANE_EN 0:Disable 1'h0 1:Enable, follow ing R_RX_LANE_SEL_EN MIPI Valid Data Lane number select 00:1Lane (lane0 Enable) 0x102D [1:0] R_RX_LANE_SEL_EN 2'h3 01,10:2Lane (lane<1:0> Enable) 11:4Lane (lane<3:0> Enable) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 7/68...
  • Page 8: Htpdn/Lockn

    R_LOCKN0_SEL 2'h0 00:Sub-Link, 01:LOCKN pin input, 10:forced Low , 11:forced High V-by-One® HS LOCKN for lane1 assignment 0x101E [1:0] R_LOCKN1_SEL 2'h0 00:Sub-Link, 01:LOCKN pin input, 10:forced Low , 11:forced High THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 8/68...
  • Page 9: V-By-One® Hs Output Setting

    00:MAP1, 01:MAP2, 10:MAP3, 11:MAP4 6.5.1 MPRF (Main-Link PRivate Format) MPRF format encoding preserves original data packet input to THCV241A and output the data packet from counterpart V-by-One® HS receiver. The counterpart receiver must have installed MPRF format decoder like THCV242 because MPRF is not standard format.
  • Page 10: V-By-One® Hs Standard Format

    Packer packet definition. Data can be transmitted normally only when both transmitter and receiver are set to the same available format. Some of the THCV241A format may not be supported by particular counterpart receiver because THCV241A prepares multiple formats that suit to multiple receiver devices alternatives.
  • Page 11 RAW[1] (2nd) V-by-One®HS_D[2] RAW[2] (3rd) R[2] R[2] (2nd) RAW[4] RAW[4] (2nd) RAW[0] (2nd) V-by-One®HS_D[1] RAW[1] (3rd) R[1] R[1] (2nd) RAW[3] RAW[3] (2nd) V-by-One®HS_D[0] RAW[0] (3rd) R[0] R[0] (2nd) RAW[2] RAW[2] (2nd) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 11/68...
  • Page 12 RAW[0] (2nd) RAW[6] (2nd) RAW[2] (2nd) V-by-One®HS_D[1] RAW[5] RAW[5] (2nd) RAW[1] (2nd) RAW[3] (2nd) RAW[5] (2nd) RAW[1] (2nd) V-by-One®HS_D[0] RAW[4] RAW[4] (2nd) RAW[0] (2nd) RAW[2] (2nd) RAW[4] (2nd) RAW[0] (2nd) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 12/68...
  • Page 13 Y[2](1st) Cr(V)[2] RAW[2] (4th) Cr(V)[2] (4th) Y[2] (4th) V-by-One®HS_D[1] Y[1] (2nd) Y[1](1st) Cr(V)[1] RAW[1] (4th) Cr(V)[1] (4th) Y[1] (4th) V-by-One®HS_D[0] Y[0] (2nd) Y[0](1st) Cr(V)[0] RAW[0] (4th) Cr(V)[0] (4th) Y[0] (4th) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 13/68...
  • Page 14 R[2] (4th) RAW[4] (2nd) RAW[4] (4th) RAW[0] (4th) V-by-One®HS_D[1] RAW[1] (7th) R[1] (2nd) R[1] (4th) RAW[3] (2nd) RAW[3] (4th) V-by-One®HS_D[0] RAW[0] (7th) R[0] (2nd) R[0] (4th) RAW[2] (2nd) RAW[2] (4th) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 14/68...
  • Page 15 RAW[6] (4th) RAW[2] (4th) V-by-One®HS_D[1] RAW[5] (2nd) RAW[5] (4th) RAW[1] (4th) RAW[3] (4th) RAW[5] (4th) RAW[1] (4th) V-by-One®HS_D[0] RAW[4] (2nd) RAW[4] (4th) RAW[0] (4th) RAW[2] (4th) RAW[4] (4th) RAW[0] (4th) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 15/68...
  • Page 16: V-By-One® Hs Output Byte Mode

    V-by-One® HS setting 00 : Reserved 0x101B [5:4] R_NHSEL 01 : Reserved 2'h3 10 : V-by-One® HS standard Low Radiation Emission mode 11 : V-by-One® HS standard High Immunity Resistance mode THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 16/68...
  • Page 17: V-By-One® Hs Output Odd/Even Swap

    Low Frequency mode format decoder like THCV236-Q. Table 15. V-by-One® HS Low Frequency Mode setting Addr(h) Bits Register w idth Description Default V-by-One® HS Low FeqModeEnable 0x101B R_LFQEN 0:Normal 1'h0 1:Low Frequency Mode THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 17/68...
  • Page 18: Target Pixel Clock

    MIPI data lane from Low Power mode to High Speed mode and from High Speed mode to Low Power mode. In addition for THCV241A, when MIPI data-rate per lane is slower than 160Mbps, horizontal blanking period length must meet below rule.
  • Page 19: Pll Setting

    Pixel clock frequency made by PLL is calculated as below. Actual Pixel clock, F(OUT) frequency must be equal or greater than ideal target Pixel clock, F(target) by 8% accuracy as below formula for most cases. THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 19/68...
  • Page 20 F(OUT) setting is not equal to F(target) if Spread Spectrum function is activated. F is supposed to be more than absolute value of applied SSCG modulation rate, |R_SPREAD|, under the condition specified on PLL constraints table. THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 20/68...
  • Page 21 0x00 0x44 0x01 1080p120fps RAW 891Mbps x4lane 2lane RAW12HF Map2 37.125 0x20 0x00 0x00 0x00 0x44 0x01 1080p120fps YUV422 1200Mbps x4lane 2lane YUV422HF Map1 0x32 0x00 0x00 0x00 0x44 0x01 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 21/68...
  • Page 22: Pll Auto Setting Function

    Register w idth Description Default PLL Auto Setting control invalid indicator 0x112F C_PLL_SET_NG 0: PLL Auto Setting control valid or PLL Manual setting mode 1: PLL Auto Setting control invalid THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 22/68...
  • Page 23: V-By-One® Hs Output Data-Rate

    30kHz +/-0.5% are exemplified below. Table 22. V-by-One® HS output SSCG R_DIVVAL setting examples (MHz) (hex.) (dec.) (kHz) F(CKI) R_DIVVAL R_DIVVAL fmod 37.125 4'hC(0xC) 24.2 4'h8(0x8) 26.4 4'h8(0x8) 23.4 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 23/68...
  • Page 24: V-By-One® Hs Crc

    THCV241A_Rev.2.11_E 6.11 V-by-One® HS CRC V-by-One® HS transmission packet payload fault or error can be detected with CRC. THCV241A generates and sends check value to receiver. For usage of CRC function, the counterpart V-by-One® receiver must have installed CRC monitor like THCV242.
  • Page 25: Mipi Packet Header V-By-One® Hs Output Bridge Mode

    Pixel Clock @R_PHMODE = 2'b00 DATA DATA @R_PHMODE = 2'b01 DATA PH3 1pixel DATA @R_PHMODE = 2'b10/11 DATA DATA Figure 6. MIPI Packet Header V-by-One® HS output bridge timing alternative THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 25/68...
  • Page 26: Mipi Virtual Channel Bridge

    When MIPI PH(Packet Header) is bridged to V-by-One® HS output with described schemes above, MIPI Virtual Channel information in PH is bridged to V-by-One® HS at the same time. Virtual Channel is supported. THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 26/68...
  • Page 27: V-By-One® Hs Vsync Generation

    Internally generated ( For example, R_VSYNC_POL=0 ) V-by-One® HS VSYNC calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16 x PCLK calculatedVS-HTOTAL x R_VS_OFFSET(=m) calculatedVS-HTOTAL x R_VS_WIDTH_LINE(=n) Figure 8. Internally generated VSYNC THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 27/68...
  • Page 28: V-By-One® Hs Hsync Generation

    HSYNC mode1 2 x PCLK 2 x PCLK 2 x PCLK Internally R_HS_MODE=11 ( For example, R_HSYNC_POL=0 ) generated HSYNC mode2 Figure 9. Internally generated HSYNC in Vertical active period THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 28/68...
  • Page 29 ( For example, R_HS_MODE=10 ) V-by-One® HS HSYNC calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16 x PCLK calculatedVS-HTOTAL x R_HS_VB_NUM(=k) in V blanking period Figure 10. Internally generated HSYNC in Vertical blanking period THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 29/68...
  • Page 30: Mipi Short Packet V-By-One® Hs Output Bridge Mode

    (FE3) (FE4) BYTE3 @R_FS_FE_SYNCEN=01 / R_VS_MODE=0 / R_VSYNC_POL=1 Vsync BYTE0 BYTE1 BYTE2 (FS1) (FS2) (FS3) (FS4) (FE1) (FE2) (FE3) (FE4) BYTE3 Figure 11. MIPI Short Packet V-by-One® HS bridge timing THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 30/68...
  • Page 31 THCV241A_Rev.2.11_E mipi Short Packet Vx1 Short Packet Figure 12. MIPI Short Packet V-by-One® HS bridge bit mapping THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 31/68...
  • Page 32: 2-Wire Serial Interface

    0: 2WIRE slv device addr. is set by AIN pin 8'd0 1: 2WIRE slv device addr. is set by follow ing register [6:0] [6:0]2WIRE slave device address value for register control THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 32/68...
  • Page 33: 2-Wire Serial Read/Write Access To Local Register

    THCV241A_Rev.2.11_E 6.17.2 2-wire serial Read/Write access to local Register HOST MPU can directly access THCV241A local register by 2-wire serial I/F. THCV241A Sub-Link Block Host Sub-Link 2-wire Master Slave Registe r MSSEL = Use r Select AIN = Use r Select Figure 13.
  • Page 34: 2-Wire Serial I/F Watch Dog Timer

    1: Interrupt (error is detected) Interrupt mask: Internal register CheckSum error 0x0061 0x00E1 R_INTM_CKSUM_ERR 1'b0 0: Interrupt mask Interrupt clear: Internal register CheckSum error 0x0062 0x00E2 R_INTC_CKSUM_ERR 1: Interrupt clear THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 34/68...
  • Page 35: Sub-Link Setting

    2: Reserved 0x0004 [1:0] R_SLINK_MODE 2'd1 3: Reserved Note: When THCV241A is used as Sub-Link Slave, this register setting has no meaning. Counterpart Sub-Link Master setting controls Sub-Link protocol including THCV241A as slave device. Sub-link Enable 0x0010 R_SLINK_EN 0:Sublink Disable...
  • Page 36 For “from remote THCV236-Q Sub-Link Master or from remote THCV242 Sub-Link mode1 or remote THCV244 Sub-Link mode1 to THCV241A Sub-Link Slave” access, “0x00FE” /”R_WB_MSB” and “R_WA_MODE” Word Address and Bank setting is required at the beginning before any read access. “0x00FE”...
  • Page 37: Sub-Link 2-Wire Set And Trigger Mode (2-Wire Normal Mode)

    Figure 16. Host MPU to Sub-Link Slave Register via THCV241A access configuration HOST MPU can access to remote side 2-wire serial slave register via THCV241A as Sub-Link Master only by THCV241A internal local register control and monitoring on 2-wire Set&Trigger mode1.
  • Page 38 When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without clock stretching. Figure 18. Sub-Link Master 2-wire slave clock stretching operation THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 38/68...
  • Page 39 16×{R_2WIRE_SCL_HW<7:0>+1} * tOSC SCL Low w idth [tLOW] setting on Sub-Link Slave side. 0x00CA [7:0] R_2WIRE_SCL_LW Output SCL Low w idth is defined as below . 8'd31 16×{R_2WIRE_SCL_LW<7:0>+1} * tOSC THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 39/68...
  • Page 40: Sub-Link Watch Dog Timer

    0x0018 0x0098 R_SLINK_WD_EN 0:Disable 1'b1 1:Enable 0x0018 0x0098 [3:2] reserved 0x0018 0x0098 [1:0] R_SLINK_WD_TIM_UP Sublink WDT time parameter 2'd0 Sublink WDT time =64×(256×R_SLINK_WD_TIM_UP<1:0> + 0x0019 0x0099 [7:0] R_SLINK_WD_TIM_DN 8'd187 R_SLINK_WD_TIM_DN<7:0>+1) ×tOSC THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 40/68...
  • Page 41: Sub-Link Interrupt Detection

    Sub-Link Slave side factor  remote 2-wire access on Sub-Link end Detectable interrupts as Sub-Link Slave are as follows.  Sub-Link Slave 2-wire master bus clear end  Sub-Link Slave 2-wire NACK detection THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 41/68...
  • Page 42: Gpio Setting

    GPIO1 Sub-Link Polling bridges output from THCV236-Q-GPIO4 Through Mode and GPIO0 Sub-Link Polling bridges output from THCV236-Q-GPIO3 Through Mode respectively. As default setting with THCV242 or THCV244 as Sub-Link Master communication (THCV241A as Sub-Link Slave), GPIO1/0 Sub-Link Polling bridges output from THCV242 or THCV244-GPIO Through Mode and GPIO3/2 Sub-Link Polling bridges input to THCV242 or THCV244-GPIO Through Mode respectively.
  • Page 43 Sub-Link device Sub-Link Polling interval Figure 19. Host MPU to Sub-Link Slave Register via THCV241A access configuration Remote UART bridge is supported with Sub-Link Polling GPIO input/output. Remote UART Tx and Rx bridge baud rate is supposed to be designed against Sub-Link Polling interval to accommodate deterministic jitter caused by intermittent Sub-Link communication timing.
  • Page 44: Register Gpio

    0x1121 [3:0] R_GPIO_INT_DETECT 0:No Interrupt 1:Interrupt (detect for asserted or negated of GPI Input) Interrupt Clear for GPI [3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0 0x1122 [3:0] R_GPIO_INTC_DETECT 0:Interrupt No Clear 1:Interrupt Clear THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 44/68...
  • Page 45: Internal Error / Status Signal Monitoring Gpio Output

    MIPI FRAMESYNC FS/FE position error 4'b1000 reserved 4'b1001 MIPI Control state error 4'b1010 MIPI FS 4'b1011 MIPI FE 4'b1100 reserved 4'b1101 reserved 4'b1110 Main-Link Data Handle error 4'b1111 PLL auto configuration setting error THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 45/68...
  • Page 46: Internal Error / Status Signal Monitoring Register

    MIPI R_RX_ECC_ERR_CRCT_CNT[15:0] R_ECC_ERR_CRCT_CNT_CLR MIPI R_RX_ECC_ERR_DBLE_CNT[15:0] R_ECC_ERR_DBLE_CNT_CLR ECC2bit error count by every Line Sub-Link R_SLINK_FBETERR_NUM_*[15:0] R_SLINK_FBETERR_CLR Sub-link Feald BET error count *H:Enable L:Disable, which is defferent polarity from other mask registers THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 46/68...
  • Page 47: Interrupt Monitoring

    [IO] INT CMOS/OpenDrain Select 0x1041 R_INT_CMOSEN 0:OpenDrain 1'h0 1:CMOS INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status may have been changed before monitoring activation. THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 47/68...
  • Page 48 This Sub-Link SLAVESIDE interrupt monitoring element connected to THCV241A Sub-Link block of THCV241A as Sub-Link Slave. MIPI, Main-Link, GPIO and other modules of THCV241A are designed as separated module and not included in Sub-Link Module so that R_INT_EXTERNAL factor must be set as “No mask” in order to report those MIPI, Main-Link, GPIO and other Interrupt factor to remote Sub-Link Master.
  • Page 49: Build-In Self-Test Pattern Generator (Bist)

    1'h0 Hbackporch pixel number = "R_HBP_V" x4 BIST Hbackporch pixel number setting 0x1071 [7:0] R_HBP_V[7:0] 8'h28 Hbackporch pixel number = "R_HBP_V" x4 0x1072 [6:0] R_VBP_V BIST Vbackporch line number 7'h10 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 49/68...
  • Page 50 Horizontal RGBW ramp × reserved × Vertical RGBW ramp × reserved × ○ 16×16 pi×el checker reserved × ○ Frame reserved × ○ Sub pixel checker reserved × reserved × reserved × THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 50/68...
  • Page 51: Main-Link Field Bet

    6.28 Main-Link Field BET In order to help users to check validity of CML serial line (Main-Link and Sub-Link), THCV241A and particular V-by-One® HS receiver have an operation mode in which they act as a bit error tester (BET). In Main- Link Field BET mode, THCV241A internally generates test pattern which is then serialized onto the Main-Link CML line.
  • Page 52: Cmos Io Input Noise Filter

    R_GPIO_TDRV 4'h0 0: Normal Drive(4mA) 1: Strong Drive(8mA) CMOS IO Drive Strength Select [6]:INT, [3]:CKO, [1]:SDA, [0]:SCL 0x1047 [6:0] R_IO_DRV[7:0] [5], [4], [2]:ReservedL 7'h00 0: Normal Drive(4mA) 1: Strong Drive(8mA) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 52/68...
  • Page 53: Cko Reference Clock Buffer Output

    CKO reference clock buffer output can be configurable by 2-wire access to internal register. Table 50. CKO setting Addr(h) Bits Register w idth Description Default CKO output source select 0x1076 R_CKOSTOP 1'h1 0:CKI, 1: Low fix THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 53/68...
  • Page 54: Soft Reset

    00 Disable(Disable Auto Soft Reset) 01 1*256*tOSC (typ.3.2us) 02 2*256*tOSC (typ.6.4us) 0x105C [7:0] R_TX_CTERM 8'h55 03 3*256*tOSC (typ.9.6us) : : FE 254*256*tOSC (typ.812.8us) FF 255*256*tOSC (typ.816us) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 54/68...
  • Page 55 R_PLL_SET_MODE=0 and R_PLL_SET_MODE=1, R_SPREAD R_DISABLE_SSCG The registers that may trigger V-by-One® HS automatic Soft Reset are as follows. R_NHSEL R_LFQEN R_ML0_PRE R_ML1_PRE R_ML0_DRV R_ML1_DRV R_COL_SEL R_COL_MAN[1:0] R_OUTPUT_FMT R_HFSEL R_BITMAP_SEL THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 55/68...
  • Page 56: Power On Sequence

    Required w ait from CKI input to PLL Enable 1000 Required w ait from PLL Lock Time to CML output F(CKI) tTPLL0 V-by-One® HS Reset Release to CML Out Delay THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 56/68...
  • Page 57: Lock / Re-Lock Sequence

    Figure 23. Re-Lock Sequence Table 54. Lock / Re-Lock Sequence specification Symbol Parameter Unit tTNP0 LOCKN=H to Training pattern output delay 1200 tTNP1 LOCKN=L to Data pattern output delay F(OUT) THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 57/68...
  • Page 58: Absolute Maximum Ratings

    Recommended Operating Conditions Symbol Parameter Condition Unit 3.3V Drive VDDH Supply Voltage (VDDIO, VDDB) 2.5V Drive 1.8V Drive VDD12 Supply Voltage 1.2V (VDDM, VDDOP, VDDL, VDDA) Operating Ambient Temperature degC THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 58/68...
  • Page 59: Consumption Current

    V-by-One® HS = 3.0Gbps x2Lane ICCW12_2 Main-link : FHD 60Hz+HDR PDN0=1, PDN1=1 ICCW33_3 27.6 MPRF (RAW10)+Distribution MIPI = 1.2Gbps x4Lane Sub-Link : active V-by-One® HS = 4.0Gbps x2Lane ICCW12_3 143.8 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 59/68...
  • Page 60 Sub-Link : active V-by-One® HS = 2227.5Mbps x2Lane ICCW12_21 121.5 Main-link :1080p120fps PDN0=1, PDN1=1 ICCW33_22 29.6 MPRF(YUV422) MIPI = 1200Mbps x4Lane Sub-Link : active V-by-One® HS = 3000Mbps x2Lane ICCW12_22 133.2 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 60/68...
  • Page 61: Dc Specifications

    Vterm-en HS mode for HS termination enable mipi D-PHY differential input impedance HS mode mipi D-PHY Single-end input high thres. LP mode mipi D-PHY Single-end input low thres. LP mode THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 61/68...
  • Page 62: Cml Transmitter Dc Specifications

    R_ML*_PRE[1:0]=01 VDDA- 1.5*VTOD R_ML*_PRE[1:0]=10 VDDA- 2*VTOD ITOZH CML Output Leak Current High R_TX_SNRST=1 ITOZL CML Output Leak Current Low R_TX_SNRST=1 R_TX_SNRST=0 ITOS CML Output Short Circuit Current or PDN0=0 VDDA=1.20v THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 62/68...
  • Page 63: Cml Bi-Directional Buffer Dc Specifications

    R_BDCZ_TERM_TX/ RX [1:0]=2'b10 CML Bi-Directional Buffer R_BDCZ_TERM_TX/ RX RTERM Termination Registance [1:0]=2'b01 R_BDCZ_TERM_TX/ RX [1:0]=2'b00 R_BDCZ_DRIVE_TX/ RX [1:0]=2'b10 CML Bi-Directional Buffer R_BDCZ_DRIVE_TX/ RX IDRIVE Drive Current [1:0]=2'b01 R_BDCZ_DRIVE_TX/ RX [1:0]=2'b00 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 63/68...
  • Page 64: Ac Specifications

    Figure 25. CML Transmitter tTRF 11.3 CML B-directional Buffer AC Specifications Table 65. CML B-directional Buffer AC Specifications Symbol Parameter Condition Unit REG0x0076/F6 tBUI Bi-Directional CML Buffer Unit Interval 128.7 137.5 172.7 = 0x15 THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 64/68...
  • Page 65: 2-Wire Serial Master/Slave Ac Specifications

    Fall time of both SDA and SCL signals bus capacitance : 400pF tSU;STO Setup time for STOP condition 0.26 *1 Please adjust Pull-up resistor and bus capacitance to meet the spec value. THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 65/68...
  • Page 66 THCV241A_Rev.2.11_E Figure 26. 2-wire serial interface timing diagram THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 66/68...
  • Page 67: Package

    0.90 Max 0.65 0.20 5.00 0.05 Max 1 PIN INDEX TOP VIEW SIDE VIEW EXPOSED PAD OPENING 3.70 0.075 PIN1 ID 0.20 R 0.40 0.40 0.20 Unit : mm BOTTOM VIEW THine Electronics, Inc. Copyright©2023 THine Electronics, Inc. SC: E 67/68...
  • Page 68: Notices And Requests

    13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

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