Frequency Counter Unit - Yaesu FT-301 Instruction Manual

FREQUENCY COUNTER UNITS
A frequency counter is incorporated for accurate
and easy frequency readout by the display diode.
The frequency readout unit consists of a counter
unit, frequency converter unit and a display unit
by LED (Light Emitting Diode) to display operat-
ing frequency in the dial window.
The counter device utilizes LED to display the
lowest digit of 100 Hz, however, the counter unit
counts to 10 Hz to avoid the annoyance of flicker
of the last digit.
The diode matrix circuit selects MHz display which
corresponds to the setting of the BAND switch.
The VFO frequency of 5 to 5.5 MHz is connected
to 13.0 - 13.5 MHz and the counter counts this
frequency.
COUNTER MIXER UNIT (PB-1541)
The heterodyne oscillator Q 2202 , 2SK19GR oscil-
lates at 18.5 MHz crystal frequency. A varactor
diode, D 2211 , 1S2209 is connected in series with a
crystal and shifts the crystal frequency to calibrate
frequency from front panel. The varactor diode
voltage is supplied through the potentiometer
marked CALIB. The oscillator output is fed through
a buffer amplifier (b 204 , 2SK19GR to the mixer,
(b 203 , SN76514 where the incoming VFO from pin
5 of printed board is heterodyned to 13.0 - 13.5
MHz signal.
The diode matrix circuit consists of a read memory
IC,
(b
201 , MSL-980Y2 and diodes D2 201 - D221o,
1 N60AM for preset counter adding 500 kHz to the
VFO frequency and for 7 MHz, 5 MHz, 1 0 MHz
and 20 MHz display.
The diodes are grounded by the BAND switch in
order to make BCD input terminal "L". The
matrix circuit is so composed that unnecessary
BCD code is grounded as BCD input of Q 2101 -
Cb1o 6 are "H" level.
Q 2106 , TIL308 is only used to display 1 or 2 for
10 MHz and 20 MHz so that A or B of BCD input
terminal is set to "H" through inverter
(b
112 ,
SN7404 for 10 or 20 MHz display.
For 5 MHz JJY or WWV signal, the counter dis-
plays 5,000 kHz, regardless of VFO frequency, by
closing gate 1 of the counter input.
The clock signal is oscillated by C MOS IC Q 22
o4,
MSM5564 which also contains 18 stages of the
binary counter. The 655.36 kHz signal is then
divided by the binary counter into a 5 Hz signal
which is amplified by a buffer amplifier
(b
205 ,
2SC3 73 and is used as a gate signal for counter gate
2.
DISPLAY LOGIC UNIT (PB-1542)
The heterodyned 13.0- 13.5 MHz signal is wave
shaped and inverted by Q 2110 , SN7404N and then
fed to gate 1 of Q 2109 , SN7400N. Gate 1 closes
when the BAND switch is set to J JY /WWV posi-
tion but opens for other positions.
Gate 2 is controlled by a 5 Hz gate signal and
counts the number of pulses passing through the
gate. The output from
(b
109 is then fed to Cb1o7 ,
SN7490N which counts 10 Hz. Q 2107 generates a
pulse each time it counts 10 pulses.
This pulse is fed to Q 2101 which displays a 100 Hz
digit. The pulse is also used as a clock pulse for
Q21o2, Cb1o3 and Cb1os to count 1 kHz, 10 kHz and
1 00 kHz pulses.
Q21o 1 - Q 2103 , TIL306 contains counter, latch
decoder, driver and LED in one package. (b 108 ,
SN74160 is used as a preset counter to add 500
kHz for such bands starting from 800 kHz. The
BCD code output from
(b
108 is fed to Cb 104 ,
TIL308. TIL308 does not contain counter circuit.
Q 2112 , SN7404N is used as inverter. A part of gate
pulse is fed to Q 2111 , SN7400N to generate reset
and memory signals.
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