Table of Contents
Advertisement
2.4 Control Signals (QSFP)
This AOC is SFF-8636 compliant. This means that the control signals shown in the pad layout support
the following functions:
Name
ModPrsL
Output
ModSelL
Input
ResetL
Input
LPMode
Input
IntL
OC output
SCL
BiDir
SDA
Bidir
The low-speed signals are Low Voltage TTL (LVTTL) compliant (except for SCL and SDA signals).
2.5 Diagnostics and Other Features
The AOC complies with the SFF-8665 specification and has the following key features:
Physical layer link optimization:
•
Programmable Tx input equalization
•
Programmable Rx output amplitude
•
Programmable Rx output pre-emphasis
Function
Module Present pin, grounded inside the module. Terminated
with pull-up in the host system. Asserted low when the
transceiver is inserted, whereby the host detects the presence of
the transceiver.
Module Select, terminated high in the module. Only when held
low by the host, the module responds to 2-wire serial
communication commands. The ModSelL enables multiple
modules to share a single 2-wire interface bus.
Reset, pulled high in the module. A low level on the ResetL pin
for longer than the minimum pulse length (t_Reset_init) initiates
a complete module reset, returning all user module settings to
their default state. During reset the host shall disregard all
status bits until the module indicates completion of the reset
interrupt by asserting IntL signal low with the Data_Not_Ready
bit negated. Note that on power up (including hot insertion) the
module completes the reset interrupt without requiring a reset.
Low Power Mode input, pulled up inside the module. The
transceiver starts up in low power mode, i.e. <1.5 W with the
two-wire interface active. The host system can read the power
class declaration from the transceiver and determine if it has
enough power to enable the high-speed operation/high power
mode of the transceiver. This can be done by asserting LPMode
low or by use of the Power_over-ride and Power_set control bits
(Address A0h, byte 93 bits 0,1).
Interrupt Low, terminated high in the host system. A "Low"
indicates a possible module operational fault or a status critical
to the host system, e.g. temperature alarm. The host identifies
the source of the interrupt using the 2-wire serial interface. The
INTL pin is de-asserted "High" after completion of reset, when
byte 2 bit 0 (Data Not Ready) is read with a value of '0'.
2-wire serial clock signal. Requires pull-up resistor to 3.3V on
host.
2-wire serial data signal. Requires pull-up resistor to 3.3V on
host.
Description
9
Advertisement
Table of Contents
