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AKM AK8446 Manual

6 channel afe with 10bit 50msps/ch adc and tg for linear ccd
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ASAHI KASEI
The AK8446 is 50MSPS/ch analogue front end IC for Linear CCD sensor, which integrates six
channels of correlated double sampling (CDS), 12-bit analog-to-digital converter, on-chip Offset
Adjust DAC, PGA, LVDS_if and Timing Genrater for CCD control.
Maximum conversion rate : 50MSPS / ch.
Input range :
Input polarity :
6ch. sampling :
Offset DAC :
PGA :
Linearity :
LVDS output :
Clock Generator
Timing Generator: CCD control clock
□ SSCG function
4 line serial interface
Power supplies :
Operation Temperature:
Power consumption :
Package:
□
MS1347-E-00
Arrow.com.
Downloaded from
6 channel AFE with 10bit 50MSPS/ch ADC and TG for Linear CCD
TG output pins
Shift pulses
Transfer pulses
Pixel rate pulses
Other pulses
Time resolution
Internal timing pulses
Time resolution
Generate sensor drive pulse (SHD, SHR, ADCK, OBP) Each ch. same setup.
Preliminary
Device Outline
Features
1.27Vpp(typ.) @ CDS mode
Negative polarity @CDS mode, Positive @DC direct mode
CDS circuit (Correlated Double Sampling)
Digital black loop compensation circuit built-in
Sensor offset compensation range = ±150 mV
Gain range: 0dB~18dB @ analog 1.5dB step ,
0~5dB @digital 0.039dB/step (7bit), separate 6 channel
Built-in auto-gain-control circuit
DNL = −1LSB(min.), +1LSB(max.) Monotone guarantee(10bit)
Data 5 pairs, Clock 1 pair
10MHz ~ 50MHz (0.2MHz step programmable)
TG1-16
10sets (SH0-9)
3sets (P0, P1, P2)
2 sets (PRS, PCL)
1 set (PWM)
Pixel rate ×1/56
SHD, SHR, ADCK, OBP
P0~3, PRS, PCL: pixel cycle x1/56, SH0~9, PWM: pixel cycle
Internal SSCG function(LVDS IF)
Accept frequency diffusion clock.
AVDD,SVDD,DVDD,QVDD: 1.7~.2.0V
AVDD3,LVDD,PVDD,TVDD: 3.0~3.6V
0°C~70°C
896mW (typ.)@6ch.mode, 50MSPS / channel
72 pin QFN with exposed thermal pad, pin pitch 0.5mm
1
[AK8446]
AK8446
2011/12/16

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Summary of Contents for AKM AK8446

  • Page 1 6 channel AFE with 10bit 50MSPS/ch ADC and TG for Linear CCD Device Outline The AK8446 is 50MSPS/ch analogue front end IC for Linear CCD sensor, which integrates six channels of correlated double sampling (CDS), 12-bit analog-to-digital converter, on-chip Offset Adjust DAC, PGA, LVDS_if and Timing Genrater for CCD control.
  • Page 2 ASAHI KASEI [AK8446] Block Diagram Reference Voltage 12bit CCDIN0 CDS / DPGA 50MSPS Clamp 4bit 7bit LVDO0P Black Loop LVDO0N SHR0 SHD0 +DAC LVDO1P 12bit CCDIN1 LVDO1N CDS / DPGA 50MSPS Clamp 4bit 7bit LVDO2P LVDO2N Black Loop SHR1 SHD1...
  • Page 3 ASAHI KASEI [AK8446] Block diagram explanation Block Function CDS/Clamp Sensor interface circuit The circuit to sample the sensor output image signal level. There are two sampling mode. CDS mode and Clamp mode. In case of the DC direct connection mode, this block is bypassed.
  • Page 4 ASAHI KASEI [AK8446] Timing The timing generation circuit Generator This block has PLL for the 56 phase generation and generates a pulse for the CCD drive and an internal-timing pulse from pixel clock (PCLK) and the TRIG signal. PCLK is reference clock of this device. PCLK and inner ADCK clock are same frequency.

  • Page 5: Pin Layout

    ASAHI KASEI [AK8446] Pin Layout 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD3 TG16 MCLK_N TG15 MCLK_P TG14 TRIG TG13 LVCK_EN TG12 RESETB TG11 SDENB TG10 SDCLK ＡＫ８４４６ SDIN...

  • Page 6: Pin Description

    ASAHI KASEI [AK8446] Pin description Name Description AVDD3 3.3V Analog power supply MCLK_N ADC sampling clock input, Pixel clock MCLK_P ADC sampling clock input, Pixel clock TRIG Line Trigger Input / Output, Each line start position indicator LVCK_EN LVCK output control (High: out) RESETB Reset pulse input.
  • Page 7 ASAHI KASEI [AK8446] Name Description TG output TG output TG output TG output TG output TVDD TG output power supply TG output TG10 TG output TG11 TG output TG12 TG output TG13 TG output TG14 TG output TG15 TG output...

  • Page 8: Functional Description

    ASAHI KASEI [AK8446] Functional Description ■ Input clock MCLK_P/N becomes the main clock, inputs the clock at LVDS level for the differential clock mode, and inputs the clock at CMOS level at the single clock mode. The pixel clock (PCLK) 10MHz~50MHz is generated with the synthesizer from 10MHz input clock.
  • Page 9 ASAHI KASEI [AK8446] ■ Input analogue signal <sensor I/F mode> There are CDS mode, clamping mode and DC direct mode as a method of sampling the input signal. Please select the mode by sensor I/F mode register. ・CDS mode A method to process the difference Vpix as its pixel level which is between the reference level Vprec of each pixel from the sensor output signal and its data level Vdata.
  • Page 10 Clamping is made in order to adjust the reference DC level of sensor signal to match the internal reference level of the AK8446. Clamp operation is controlled by SHR. Clamp switch closes during SHR = High , and CCDINn ( n = 0 ~ 5 ) pin signal is pulled toward the internal clamp level. SHR...
  • Page 11 ASAHI KASEI [AK8446] ■ ADC A/D Converter The 12-bit 50 MSPS ADC on each of the six channels converts the offset- and gain-adjusted Image signal level to digital data. The ADC output is in straight binary code, with an output strength of 0000h for black input (0 Vpp) and FFFFh for white input (maximum input).
  • Page 12 ASAHI KASEI [AK8446] Black correction timing example loop off TRIG(input) OBP(internal TG timing) TG timing program loop on valid pixel data Analog Digital Black setting reg. The loop works to Black adjust here to 0. It is possible to control black loop according to the OBP signal. OBP set to "H" where in the effective data section at CCD black level output.
  • Page 13 ASAHI KASEI [AK8446] ■AGC (Auto Gain Control) The range of the peak detection in one line is set in the register, and the peak is detected at the range setting. The range of the peak detection sets peak detection beginning position/end position...
  • Page 14 ASAHI KASEI [AK8446] Auto gain control sequence MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from...
  • Page 15 ASAHI KASEI [AK8446] It is a circuit that generates CLK for LVDS buffer from input clock ADCK. Serializer & LVDS The Serializer composes the 12-bit bandwidth output data from each ADC into LVDS serial data lines. LVDO0 LVDO1 LVDO2 LVDO3...
  • Page 16 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from...
  • Page 17 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from...
  • Page 18 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from...
  • Page 19 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from...
  • Page 20 ASAHI KASEI [AK8446] Reset When starting a power, the value of the register is unsettled including the register for the test. Reset immediately after starting a power to avoid influencing usual operation by the register for the test. When RESETB pin is Low, a register is reset, and each register is set a default value and the register for the test is set for the normal operation.
  • Page 21 ASAHI KASEI [AK8446] Absolute Maximum Ratings All voltages are referenced to ground. item symbol Min. Max. unit note Power Supplies AVDD Analog(1.8V) Synthesizer SVDD TG PLL QVDD Digital DVDD −0.3 Analog(3.3V) AVDD3 LVDS PLL PVDD LVDS LVDD TG output TVDD −10...
  • Page 22 ASAHI KASEI [AK8446] Electrical Characteristics Digital DC Characteristics (AVDD=SVDD=QVDD=DVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V, Ta= 0~70°C) Item Symbol Min. Max. Unit Remark 0. 7*AVDD3 High level input threshold 0. 3*AVDD3 Low level input threshold High level output 0.8*TVDD IOH=－1mA voltage Low level output 0.2*TVDD...
  • Page 23 VODP VODN LVCKN / LVDOxN VOSP VOSN ASAHI KASEI [AK8446] LVDS input DC Characteristics (AVDD=SVDD=QVDD=DVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V, Ta= 0~70°C) Item Symbol Conditions min. typ. max. Unit Input common Signal level not rise above level(fig.) 0～2.4V ±100 ±600 Differential Input VIC = 1.2V Range(fig.)
  • Page 24 ASAHI KASEI [AK8446] 5) Switching Characteristic Synthesizer in use , Ta= 0~70°C) AVDD=SVDD=QVDD=DVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V Item Symbol Conditions min. typ. max. Unit Main clock frequency Fref Main clock period Tref Fpix (note 1) • Range of frequency multiplying Step of frequency Pstep 0.18...
  • Page 25 ASAHI KASEI [AK8446] Pixel clock input at the slave mode Item Symbol Conditions min. typ. max. Unit External input TRIG(@ external input) setup time External input TRIG(@ external input) hold time Pixel Clock TRIG MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 26 ASAHI KASEI [AK8446] ■ MCLK, Pixel clock, TRIG timing MCLK_P TRIG The frequency is decided to pixel CLK(PCLK) by MCLK_P depending on x frequency setting value. Pixel Clock Internal TRIG Pixel counter ･･･ Please input an active section of 3CLK or more to TRIG with MCLK_P.
  • Page 27 ASAHI KASEI [AK8446] ■ 56 phase counter, internal SHR, SHD, ADCK timing. (AVDD=SVDD=QVDD=DVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V, Ta= 0~70°C) Item Symbol Conditions min. typ. max. Unit TG minimum width TGWID (note 1) 6.07 SHD, SHR PSTR (note 1) phase start position SHD, SHR...
  • Page 28 ASAHI KASEI [AK8446] ■Internal OBP Timing i : falling position j : rising position The internal timing of OBP is shown here, with i as the falling position and j as the rising position. Please input a black pixel from the High section of the OBP monitor pulse in front of 5.5 clocks of ADCK about the input for the OBP period to AFE.
  • Page 29 ASAHI KASEI [AK8446] ■ Output timing ( @ SSCG function OFF) The input data is converted AD by ADCK Clock which is generated by the output of 56 phase generator PLL and it is output on LVDS outputs. It is output delaying 15CLK in the ADCK standard.
  • Page 30 ASAHI KASEI [AK8446] LVDS Output timing Tlcyc Tlvh Tlvl LVCKP- LVCKN Vdiff=0V LVDOxP- LVDOxN Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 (x=0 ~ 4) Item Symbol min. typ. max. Unit Tlcyc 0.5Tcyc LVDS clock Tlcyc= +0.2 －0.2 Tlcyc Tlcyc Tlcyc...
  • Page 31 ASAHI KASEI [AK8446] ■ PLL start up timing It moves from synthesizer PLL, PLL for TG, and PLL for LVDS after the following sequences after power down release at normal operation for prevention from PLL incorrect lock. Please do power down at the time of frequency change.
  • Page 32 ASAHI KASEI [AK8446] Switching Characteristics Serial i/f (AVDD=SVDD=QVDD=DVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V, Ta= 0~70°C) Item Symbol Min. Typ. Max. Unit Condition Clock frequency Scyc SDCLK Clock high width SDCLK Clock low width SDCLK Setup time SDIN (referenced to SDCLK) SDENB Hold time SDIN...
  • Page 33 ASAHI KASEI [AK8446] ■Reset Trst1 0.9×AVDD3 Power Trst2 RESETB LVCK_EN=L AVDD=SVDD=QVDD=DVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V, Ta= 0~70 ° C) Item Symbol Min. Typ. Max. Unit Condition Reset period 1 Trst1 RESETB Reset period 2 Trst2 RESETB LVCK_EN=H AVDD=SVDD=QVDD=DVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V, Ta= 0~70 ° C)
  • Page 34 ASAHI KASEI [AK8446] 6) SSCG Characteristic Use SSCG on LVDS Synthesizer MCLK LVDS TG PLL LVDS PLL (56 phase PLL) (ＬＶＤＳ phase PLL) 7 phase PLL1 SSCG ON SSCG OFF PLL2 PLL3 ＴＧ TG PLL Frequency character Item Unit Condition...
  • Page 35 ASAHI KASEI [AK8446] Analog Characteristics (SVDD=AVDD=DVDD=QVDD=1.7~2.0V, AVDD3=PVDD=LVDD=TVDD=3.0~3.6V, Ta= 25°C) Item Symbol Condition Unit Reference Voltage Block VCLP 2.166 2.436 Clamp voltage DC direct mode reference voltage Clamp and CDS Block Input range PGA gain = 0dB setting 1.13 1.27 1.43 CDS mode 1.07...
  • Page 36 ASAHI KASEI [AK8446] Noise , Internal offset, Crosstalk No input noise PGA gain=0dB (note 3) PGA gain=18dB Crosstalk XTALK1 (note 5) XTALK2 (note 6) Black calibration Block BCBW1 1 time speed (default) 8192 clock Black calibration BCBW2 5461 times speed (max.)
  • Page 37 ASAHI KASEI [AK8446] [CCD Timing Generator] TG1~16 TG output pin It is a TG signal output terminal connected to CCD. All of these terminals are the internal signal of TG, a register sets one among SH0~9, P0, P1, P2,PRS, PCL, OBP,PWM voluntarily and can output it.
  • Page 38 ASAHI KASEI [AK8446] 90 91 92 Follow page 93 94 95 96 97 98 99 100 102 103 104 105 110 111 112 113 117 118 118 120 19, 20,21,22,23,24, 25,26,27,28 29, 30, 31,32,33,34, 35,36,37,38 39, 40, 41, 42, 43,44...
  • Page 39 ASAHI KASEI [AK8446] **Timing of 1~96 can be set between 1 ~ 2 Pixels. ( But 9~52 and 61~84 are set 10bit from 1 of P0_END position.) The TG signal for CCD is 15 kinds of P0, P1, P2, PCL, PRS, SH0~9 inside the LSI.
  • Page 40 ASAHI KASEI [AK8446] Serial interface Write into AK8446 SDCLK SDIN A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 High Z SDOUT SDENB Fig. 1 Write into Register When clock ( SDCLK ) and Data ( SDIN ) are fed without raising SDENB signal to high after the first data is written, data is written in every 8 bit at the address location which is a previous data address + 1 location until SDENB is set to high.
  • Page 41 ASAHI KASEI [AK8446] Control Register (Address Map) Register Map Bits Default Register Function Adrs Value Name 0000*** BANK[3:0] Bank bit setting *******0 SRSTN Internal reset signal Bank 0 Bits Default Register Function Adrs Value Name *0******** CLKMODE Clock mode select...
  • Page 42 ASAHI KASEI [AK8446] 00000000 LVDS_T_FIX[7:0] LVDS fixed pattern setting 00****** LVDS_FORMAT[1:0] LVDS Format select **0***** LVDS_POL LVDS polarity setting ***0**** FIFO_ON FIFO select ****0*** TRIG_MODE Master/Slave mode select *****0***** LOOPOFF Black Loop ON/OFF setting ***0* LOOPDACOFF DAC operation with black boost...
  • Page 43 ASAHI KASEI [AK8446] Bank １ Bits Default Register Function Adrs Value Name 0******* TRIG_POL TRIG polarity setting *1****** TG_EN TG output enable **00**** DRVTG1[1:0] TG1 output drivability ****0*** INVTG1 TG1 output invert *****000 SEL TG1[2:0] TG1 output setting **00**** DRVTG2[1:0]...
  • Page 44 ASAHI KASEI [AK8446] **00**** DRVTG13[1:0] TG13 output drivability ****0*** INVTG13 TG13 output invert *****000 SELTG13[2:0] TG13 output setting **00**** DRVTG14[1:0] TG14 output drivability ****0*** INVTG14 TG14 output invert *****000 SELTG14[2:0] TG14 output setting **00**** DRVTG15[1:0] TG15 output drivability ****0*** INVTG15...
  • Page 45 ASAHI KASEI [AK8446] Bank ２ Bits Default Register Function Adrs Value Name 1110**** PRSR[15:12] PRS rise timing 3 setting ****1110 PRSR[11:8] PRS rise timing 2 setting 1110**** PRSR[7:4] PRS rise timing 1 setting ****1110 PRSR[3:0] PRS rise timing 0 setting...
  • Page 46 ASAHI KASEI [AK8446] Bank 3 Bits Default Register Function Adrs Value Name ******00 P0_RISE0[9:8] P0 clock rise position 0 setting 00000000 P0_RISE0[7:0] P0 clock rise position 0 setting ******00 P0_FALL0[9:8] P0 clock fall position 0 setting 00000000 P0_FALL0[7:0] P0 clock fall position 0 setting...
  • Page 47 ASAHI KASEI [AK8446] Bank 4 Bits Default Register Function Adrs Value Name ******00 P1_RISE0[9:8] P1 rise position 0 setting 00000000 P1_RISE0[7:0] P1 rise position 0 setting ******00 P1_FALL0[9:8] P1 fall position 0 setting 00000000 P1_FALL0[7:0] P1 fall position 0 setting...
  • Page 48 ASAHI KASEI [AK8446] Bank 5 Bits Default Register Function Adrs Value Name ******00 P2_RISE0[9:8] P2 rise position 0 setting 00000000 P2_RISE0[7:0] P2 rise position 0 setting ******00 P2_FALL0[9:8] P2 fall position 0 setting 00000000 P2_FALL0[7:0] P2 fall position 0 setting...
  • Page 49 ASAHI KASEI [AK8446] Bank 6 Bits Default Register Function Adrs Value Name *******0 PWM_ENABLE PWM pulse enable **000000 PWM_ST[13:8] PWM pulse period setting 00000000 PWM_ST[7:0] PWM pulse period setting **000000 PWM_END[13:8] PWM pulse Hi width setting 00000000 PWM_END[7:0] PWM pulse Hi width setting...
  • Page 50 ASAHI KASEI [AK8446] Bank 7 Bits Default Register Function Adrs Value Name ******00 SH1Rise0[9:8] SH1 rise position 0 00000000 SH1Rise0[7:0] SH1 rise position 0 ******00 SH1Fall0[9:8] SH1 fall position 0 00000000 SH1Fall0[7:0] SH1 fall position 0 ******00 SH1Rise1[9:8] SH1 rise position 1...
  • Page 51 ASAHI KASEI [AK8446] Bank 8 Bits Default Register Function Adrs Value Name ******00 SH2Rise0[9:8] SH2 rise position 0 00000000 SH2Rise0[7:0] SH2 rise position 0 ******00 SH2Fall0[9:8] SH2 fall position 0 00000000 SH2Fall0[7:0] SH2 fall position 0 ******00 SH2Rise1[9:8] SH2 rise position 1...
  • Page 52 ASAHI KASEI [AK8446] Bank 9 Bits Default Register Function Adrs Value Name ******00 SH4Rise0[9:8] SH4 rise position 0 00000000 SH4Rise0[7:0] SH4 rise position 0 ******00 SH4Fall0[9:8] SH4 fall position 0 00000000 SH4Fall0[7:0] SH4 fall position 0 ******00 SH4Rise1[9:8] SH4 rise position 1...
  • Page 53 ASAHI KASEI [AK8446] Bank 10 Bits Default Register Function Adrs Value Name ******00 SH6Rise0[9:8] SH6 rise position 0 00000000 SH6Rise0[7:0] SH6 rise position 0 ******00 SH6Fall0[9:8] SH6 fall position 0 00000000 SH6Fall0[7:0] SH6 fall position 0 ******00 SH6Rise1[9:8] SH6 rise position 1...
  • Page 54 ASAHI KASEI [AK8446] Bank 11 Bits Default Register Function Adrs Value Name ******00 SH9Rise0[9:8] SH9 rise position 0 00000000 SH9Rise0[7:0] SH9 rise position 0 ******00 SH9Fall0[9:8] SH9 fall position 0 00000000 SH9Fall0[7:0] SH9 fall position 0 ******00 SH9Rise1[9:8] SH9 rise position 1...
  • Page 55 ASAHI KASEI [AK8446] Address 00H (RESET : 0000 ***0) Bank setting register BANK[3:0] Bank 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Inhibited 1101 Inhibited 1110 Inhibited 1111 Inhibited Soft reset SRST_N Soft reset ０...
  • Page 56 ASAHI KASEI [AK8446] Bank 0 Address 01H (RESET : *010 0010) Sensor mode CLKMODE Sensor mode Pixel clock input mode Synthesizer mode Frequency Range Select PFRNG[1:0] Frequency Range Select 10MHz-16MHz 16MHz-25MHz 25MHz-50MHz Inhibited Sensor mode select SENS_MODE[1:0] Sensor mode DC direct ＣＤＳ...
  • Page 57 ASAHI KASEI [AK8446] Bank 0 Address 02H (RESET : 0011 0001) Synthesizer output frequency setting register SYN_FRNG[7:0] Frequency setting 0000 0000 Inhibition ・・・ ・・・ 0011 0000 Inhibition 0011 0001 49 (1.00 times) 0011 0010 50 (1.02 times) ・・・ ・・・ 1111 1000 248 (4.98 times)
  • Page 58 ASAHI KASEI [AK8446] Bank 0 Address 03H (RESET : 0000 0000) Clamp bandwidth setting CLP_BW[1:0] Clamp bandwidth 2040us Inhibition Inhibition 5.9us (note) When using capacitor of 0.1uF to CCDIN and the REFIN pin. Spread-frequency mode(note1) SSCG_MODE[5:4] Spread clock mode Internal spread OFF...
  • Page 59 ASAHI KASEI [AK8446] Bank 0 Address 04H~09H (RESET: **00 0000) CCDIN* offset setting register OFF* [5:0] offset +252.16 ｍＶ 01 1111 +244.03 ｍＶ 01 1110 ・・・ ・・・ +8.13 ｍＶ 00 0001 00 0000 ０ －8.13 ｍＶ 11 1111 ・・・ ・・・...
  • Page 60 ASAHI KASEI [AK8446] Bank 0 Address 0DH~12H (RESET: *000 0000) Bank 0 Address 0DH (bit7) Auto gain control beginning flag AUTOGAIN_TRIG Auto gain control beginning flag ０ Auto gain control function Disable １ Auto gain control function Enable Bank 0 Address 0EH (bit7)
  • Page 61 ASAHI KASEI [AK8446] Bank 0 Address 14H (RESET: *000 0000) ＬＶＤＳ output level register setting ＬＶＤＳ level setting LVDS_LVL ３５０ｍＶ ２００ｍＶ ＬＶＤＳ test pattern setting register ＬＶＤＳ test pattern setting LVDS_TST[3:0] 0000 Normal output 0001 Inhibition 0010 Inhibition 0011 Random pattern output...
  • Page 62 ASAHI KASEI [AK8446] LVDS_TST=”1010” LVDS Worst Pattern L V C K L V D L V D L V D L V D L V D LVDO3 and LVDO4 become Hi-Z outputs at LVDS_PTN=“00/01". ＬＶＤＳ test pattern 1 selection register...
  • Page 63 ASAHI KASEI [AK8446] Bank 0 Address 16H (RESET: 0000 0000) LVDS Format setting register ＬＶＤＳ Format LVDS_FORMAT[1:0] Inhibition LVDS polarity setting register ＬＶＤＳ polarity LVDS_POL Normal Ｐ, Ｎ reversal FIFO selection register FIFO_ON FIFO ０ FIFO OFF １ FIFO ON...
  • Page 64 ASAHI KASEI [AK8446] Bank 0 Address 17H (RESET: 0000 0000) Black level setting BLKLVL[7:0] Decimal code 0000 0000 0000 0001 ・・・ ・・・ 1100 0110 1100 0111 Inhibition ・・・ ・・・ 1111 1110 Inhibition 1111 1111 Inhibition Bank 0 Address 18H (RESET: 0000 0000)
  • Page 65 ASAHI KASEI [AK8446] Bank 0 Address 19H (RESET: 0000 0000) Black Loop band width during boost ＢＢＳＴ Black Loop band width during boost ００００ 8192 times ０００１ 4096 times ００１０ 2048 times ００１１ 1024 times ０１００ 512 times ０１０１ 256 times ０１１０...
  • Page 66 ASAHI KASEI [AK8446] Bank 0 Address 1AH (RESET: *000 0000) Auto gain control ON / OFF select AUTOGAIN Auto gain control setting Off (register value is effective for a gain.) Auto gain average period setting AGC_AVERAGE[2:0] Average period 1024 AGC wait counter setting...
  • Page 67 ASAHI KASEI [AK8446] Bank 0 Address 1CH (RESET: 0000 0000) Bank 0 Address 1DH (RESET: 0000 0000) Address 1CH (bit7:6) AGC error distinction threshold code setting AGC_ERR_CODE[1:0] Error distinction threshold code ００ ±5LSB ０１ ±10LSB １０ ±20LSB １１ ±40LSB Auto gain control Start Flag...
  • Page 68 ASAHI KASEI [AK8446] Bank 1 Address 01H (RESET: 0100 0000) TRIG polarity (Slave mode) TRIG_POL ０ Normal polarity １ Reversal Normal P i x e l c l o c k T R I G M a i n c o u n t e r …...
  • Page 69 ASAHI KASEI [AK8446] Bank 1 Address 02H (RESET: **00 0000) TG2 output drive capacity DRVTG2[1:0] Normal capacity ×２ ×３ ×４ TG2 polarity INVTG2 Normal polarity Reversal TG2 output selection SEL TG2[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com.
  • Page 70 ASAHI KASEI [AK8446] Bank 1 Address 03H (RESET: **00 0000) TG3 output drive capacity DRVTG3[1:0] Normal capacity ×２ ×３ ×４ TG3 polarity INVTG3 Normal polarity Reversal TG3 output selection SELTG3[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 71 ASAHI KASEI [AK8446] Bank 1 Address 04H (RESET: **00 0000) TG4 output drive capacity DRVTG4[1:0] Normal capacity ×２ ×３ ×４ TG4 polarity INVTG4 Normal polarity Reversal TG4 output selection SELTG4[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 72 ASAHI KASEI [AK8446] Bank 1 Address 05H (RESET: **00 0000) TG5 output drive capacity DRVTG5[1:0] Normal capacity ×２ ×３ ×４ TG5 polarity INVTG5 Normal polarity Reversal TG5 output selection SELTG5[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 73 ASAHI KASEI [AK8446] Bank 1 Address 06H (RESET: **00 0000) TG6 output drive capacity DRVTG6[1:0] Normal capacity ×２ ×３ ×４ TG6 polarity INVTG6 Normal polarity Reversal TG6 output selection SELTG6[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 74 ASAHI KASEI [AK8446] Bank 1 Address 07H (RESET: **00 0000) TG7 output drive capacity DRVTG7[1:0] Normal capacity ×２ ×３ ×４ TG7 polarity INVTG7 Normal polarity Reversal TG7 output selection SELTG7[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 75 ASAHI KASEI [AK8446] Bank 1 Address 08H (RESET: **00 0000) TG8 output drive capacity DRVTG8[1:0] Normal capacity ×２ ×３ ×４ TG8 polarity INVTG8 Normal polarity Reversal TG8 output selection SELTG8[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 76 ASAHI KASEI [AK8446] Bank 1 Address 09H (RESET: **00 0000) TG9 output drive capacity DRVTG9[1:0] Normal capacity ×２ ×３ ×４ TG9 polarity INVTG9 Normal polarity Reversal TG9 output selection SELTG9[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 77 ASAHI KASEI [AK8446] Bank 1 Address 0AH (RESET: **00 0000) TG10 output drive capacity DRVTG10[1:0] Normal capacity ×２ ×３ ×４ TG10 polarity INVTG10 Normal polarity Reversal TG10 output selection SELTG10[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 78 ASAHI KASEI [AK8446] Bank 1 Address 0BH (RESET: **00 0000) TG11 output drive capacity DRVTG11[1:0] Normal capacity ×２ ×３ ×４ TG11 polarity INVTG11 Normal polarity Reversal TG11 output selection SELTG11[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 79 ASAHI KASEI [AK8446] Bank 1 Address 0CH (RESET: **00 0000) TG12 output drive capacity DRVTG12[1:0] Normal capacity ×２ ×３ ×４ TG12 polarity INVTG12 Normal polarity Reversal TG12 output selection SELTG12[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 80 ASAHI KASEI [AK8446] Bank 1 Address 0DH (RESET: **00 0000) TG13 output drive capacity DRVTG13[1:0] Normal capacity ×２ ×３ ×４ TG13 polarity INVTG13 Normal polarity Reversal TG13 output selection SELTG13[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 81 ASAHI KASEI [AK8446] Bank 1 Address 0EH (RESET: **00 0000) TG14 output drive capacity DRVTG14[1:0] Normal capacity ×２ ×３ ×４ TG14 polarity INVTG14 Normal polarity Reversal TG14 output selection SELTG14[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 82 ASAHI KASEI [AK8446] Bank 1 Address 0FH (RESET: **00 0000) TG15 output drive capacity DRVTG15[1:0] Normal capacity ×２ ×３ ×４ TG15 polarity INVTG15 Normal polarity Reversal TG15 output selection SELTG15[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 83 ASAHI KASEI [AK8446] Bank 1 Address 10H (RESET: **00 0000) TG16 output drive capacity DRVTG16[1:0] Normal capacity ×２ ×３ ×４ TG16 polarity INVTG16 Normal polarity Reversal TG16 output selection SELTG16[2:0] Lo fix output Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 84 ASAHI KASEI [AK8446] Bank 1 Address 11H (RESET: **00 *000) TEST output drive capacity DRVTGTEST[1:0] Normal capacity ×２ ×３ ×４ TEST output selection SELTEST [2:0] Lo fix output Hi fix output Inhibition Inhibition Inhibition Inhibition MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com.
  • Page 85 ASAHI KASEI [AK8446] TG output list SELTG*[2:0] / SELTEST[2:0] 出力ピン Inhibition Inhibition Inhibition Inhibition Inhibition Inhibition Inhibition Inhibition Inhibition Inhibition TG10 Inhibition TG11 Inhibition TG12 Inhibition TG13 Inhibition TG14 Inhibition TG15 Inhibition TG16 Inhibition TEST Inhibition Inhibition Inhibition MS1347-E-00 2011/12/16 Arrow.com.
  • Page 86 ASAHI KASEI [AK8446] Bank 1 Address 12H (RESET: *000 *000) (RESET: **** *000) P0,P1,P2 pattern selection P*_PTN[2:0] P0,P1,P2 pattern selection ０００ Normal output Ｈａｌｆ output Pattern 1 １００ Ｈａｌｆ output Pattern 2 １０１ Ｈａｌｆ output Pattern 3 １１０ Ｈａｌｆ output Pattern 4 １１１...
  • Page 87 ASAHI KASEI [AK8446] Bank 1 Address 14H~16H,18H~1AH,1CH~1EH (RESET: 1110 1110) Address 17H, 1BH, 1FH (RESET: 1110 0000) Bank 2 Address 01H~03H (RESET: 1110 1110) Address 04H (RESET: 1110 0000) P0, P1, P2, PRS Rise/Fall position setting register [3:0] Rise 0/Fall 0...
  • Page 88 ASAHI KASEI [AK8446] Bank 2 Address 05H~0AH Rise timing (RESET: **11 1111) Fall timing (RESET: **00 0000) PCL,SHR,SHD Rise/Fall position setting register [5:0] Rise /Fall [5:0] Rise /Fall ００ ００００ ０ １０ ０１００ ３２ ００ ０００１ １ １０ ０１０１ ３３...
  • Page 89 ASAHI KASEI [AK8446] Bank 2 Address 0BH (RESET: **00 0000) ADCK Rise/Fall position setting register [5:0] Rise / Fall [5:0] Rise / Fall ００ ００００ ０ １０ ０１００ ３２ ００ ０００１ １ １０ ０１０１ ３３ ００ ００１０ ２ １０ ０１１０...
  • Page 90 ASAHI KASEI [AK8446] Bank 2 Address 0CH, 0DH (Reset clock start) 0EH, 0FH (Reset clock stop) 10H, 11H (Clamp clock start) 12H, 13H (Clamp clock stop) 14H, 15H (P0 clock start) 16H, 17H (P0 clock stop) 18H, 19H (P1 clock start)
  • Page 91 ASAHI KASEI [AK8446] Bank 6 Address 01H (Reset: **** ***0) PWM pulse enable PWM_ENABLE PWM enable ０ PWM：Disable PWM：Enable １ PCLK PWM_ENABLE PWM pulse output after PWM_EN setting PWM_END PWM_ST (note) Please set PWM_ST and PWM_END by using Bank 6 Address 02H~05H.
  • Page 92 ASAHI KASEI [AK8446] Bank 6 Address 06H, 07H (SH0 rise position 0 setting) 08H, 09H (SH0 fall position 0 setting) 0AH, 0BH (SH0 rise position 1 setting) 0CH, 0DH (SH0 fall position 1 setting) 0EH, 0FH (SH0 rise position 2 setting)
  • Page 93 ASAHI KASEI [AK8446] Bank 9 Address 01H, 02H (SH4 rise position 0 setting) 03H, 04H (SH4 fall position 0 setting) 05H, 06H (SH4 rise position 1 setting) 07H, 08H (SH4 fall position 1 setting) 09H, 0AH (SH4 rise position 2 setting)
  • Page 94 ASAHI KASEI [AK8446] Bank 11 Address 09H, 0AH (SH Internal rise position 0 setting) 0BH, 0CH (SH Internal fall position 0 setting) 15H, 16H (EN Internal rise position 1 setting) 17H, 18H (EN Internal fall position 1 setting) SH Internal［13：0］/EN Internal［13：0］...
  • Page 95 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 96 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 97 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 98 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 99 ASAHI KASEI [AK8446] Bank 11 Address 1CH (Reset: **00 0000) Address 1DH (Reset: 0000 0000) PIXEL［13：0］ PIXEL 00 0000 0000 0000 00 0000 0000 0001 ・・・ ・・・ 11 1111 1111 1110 16382 11 1111 1111 1111 16383 Bank 11 Address 1EH (Reset: 0000 0001) BOS_RISE［13：0］...
  • Page 100 ASAHI KASEI [AK8446] External Circuit Examples ■Analog pins 0.1uF CCDIN0～5 8.2kΩ AISET VRP_CAP VCLP 33nF CAPPLL1 100nF CAPPLL2 4.7nF CAPPLL3 When use LVDS SSCG function, please use the following parts of CAPPLL3 470pF CAPPLL3 15kΩ 47nF Resistance accuracy: ±1%, CAP accuracy:±20% (temperature characteristics)
  • Page 101 ASAHI KASEI [AK8446] ■Power pins *1= AVDD 0.1uF AVDD3 *VDD(*1） DVDD 10uF PVDD SVDD QVDD TVDD LVDD MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 102 ASAHI KASEI [AK8446] ■LVDS output pins LVDOxP (x=0-5) 100Ω LVDOxN (x=0-5) LVCKP 100Ω LVCKN ■SDOUT pins 10kΩ SDOUT MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 103 ASAHI KASEI [AK8446] Packages MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 104 Marking (1) #1 pin identifier : Chamfered corner (2) Marketing code : AK8446 (3) Date code : XXXXXXX (7 digit) Upper 4 digit : week code Lower 3 digit : AKM’s control code AK8446 XXXXXXX MS1347-E-00 2011/12/16 Arrow.com. Arrow.com. Arrow.com.

  • Page 105: Important Notice

    AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
  • Page 106 Confidential ASAHI KASEI [AK8446] 20120906 MS1347-E00 AK8446E102_111215.DOC をベースに作成。J00 に合わせる Rev.1.02 2011/12/16 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.