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AKM AK4588 Manual

2/8-channel audio codec with dir
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ASAHI KASEI
The AK4588 is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. The AK4588 has a dynamic
range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car
audio. The AK4588 also has the balance volume control corresponding to the Dolby Digital (AC-3)
system.
The also has digital audio receiver (DIR) and transmitter (DIT) compatible with 192kHz, 24bits. The DIR
has 8-channel input selector and can automatically detect a Non-PCM bit stream. The AK4588 provides
a fully compatibility of hardware and software with the AK4628 and the AK4114.
*AC-3 is a trademark of Dolby Laboratories.
ADC/DAC part
2ch 24bit ADC
8ch 24bit DAC
High Jitter Tolerance
Extenal Master Clock Input:
Rev0.9
AKM CONFIDENTIAL
= Preliminary =
2/8-Channel Audio CODEC with DIR
GENERAL DESCRIPTION
FEATURES
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- Overflow flag
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- Zero Detect Function
- 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
- 128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
- 128fs (fs=120kHz ∼ 192kHz)
- 1 -
[AK4588]
AK4588
2003/09

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Summary of Contents for AKM AK4588

  • Page 1 GENERAL DESCRIPTION The AK4588 is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range.
  • Page 2 AKM CONFIDENTIAL ASAHI KASEI [AK4588] DIR/DIT Part AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible Low jitter Analog PLL PLL Lock Range : 32kHz to 192kHz Clock Source: PLL or X'tal 8-channel Receiver input 2-channel Transmission output (Through output or DIT) Auxiliary digital input De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz...
  • Page 3 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Block Diagram PVSS PVDD X'tal Clock Oscillator 8 to 3 Recovery Clock MCKO1 Generator Input MCKO2 Selector LRCK2 DAIF Audio BICK2 Decoder SDTO2 DAUX2 AVDD AVSS DVDD Error & CCLK Q-subcode DVSS AC-3/MPEG µP I/F...
  • Page 4 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Ordering Guide -10 ∼ +70°C AK4588VQ 80pin LQFP(0.5mm pitch) AKD4588 Evaluation Board for AK4588 Pin Layout TEST1 INT1 BOUT TVDD DVDD AVSS DVSS AVDD VREFH VCOM (Top View) TEST3 MCKO2 MCKO1 COUT ROUT1 UOUT VOUT...
  • Page 5 (I2C=”H”) AK4114: Set by CAD1/0 pins DIR/DIT part: Fixed to “00” (*) The AK4588 has two register maps including ADC/DAC part (compatible with the AK4588) and DIR/DIT part (compatible with AK4114). Each register is selected by Chip Address. Rev0.9 2003/09...
  • Page 6 ASAHI KASEI AKM CONFIDENTIAL [AK4588] PIN/FUNCTION Pin Name Function INT1 Interrupt 1 Pin Block-Start Output Pin for Receiver Input BOUT “H” during first 40 flames. TVDD Output Buffer Power Supply Pin, 2.7V∼5.5V DVDD Digital Power Supply Pin, 3.3V DVSS Digital Ground Pin...
  • Page 7 [AK4588] Pin Name Function Power-Down Mode Pin When “L”, the AK4588 is powered-down, all output pin goes “L”, all registers are reset. When CAD1/0 pins are changed, the AK4588 should be reset by PDN pin. Master Mode Select Pin MASTER “H”: Master mode, “L”: Slave mode...
  • Page 8 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Pin Name Function AVDD Analog Power Supply Pin, 4.5V∼5.5V Analog Ground Pin, 0V AVSS Receiver Channel 0 Pin (Internal biased pin) This channel is default in serial mode. No Connect This pin should be connected to PVSS.

  • Page 9: Recommended Operating Conditions

    7. The power up sequence between AVDD, DVDD, PVDD and TVDD is not critical. To save leak current in power down mode, AVDD, DVDD, PVDD become the same voltage as much as possible. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. Rev0.9...

  • Page 10: Analog Characteristics

    AKM CONFIDENTIAL ASAHI KASEI [AK4588] ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, unless otherwise specified) Parameter Units ADC Analog Input Characteristics...

  • Page 11: Filter Characteristics

    AKM CONFIDENTIAL ASAHI KASEI [AK4588] Notes: 8. S/N measured by CCIR-ARM is 96dB(@fs=48kHz). 9. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 10. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).
  • Page 12 AKM CONFIDENTIAL ASAHI KASEI [AK4588] DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD=4.5∼5.5V; TVDD=2.7∼5.5V) Parameter Symbol Units High-Level Input Voltage (Except XTI pin) (XTI pin) 70%DVDD Low-Level Input Voltage (Except XTI pin) (XTI pin) 30%DVDD Input Voltage at AC Coupling (XTI pin)
  • Page 13 1/fs Notes: 18. “L” time at I S format. 19. The AK4588 can be reset by bringing PDN “L” to “H” upon power-up. 20. These cycles are the number of LRCK rising from PDN rising. Rev0.9 2003/09 - 13 -...
  • Page 14 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Parameter Symbol Units Audio Interface Timing (Slave Mode) TDM0= “0” , TDM1= “0” BICK1 Period tBCK BICK1 Pulse Width Low tBCKL Pulse Width High tBCKH LRCK1 Edge to BICK1 “↑” (Note 21) tLRB BICK1 “↑” to LRCK1 Edge...
  • Page 15 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Timing Diagram(ADC/DAC part) 1/fCLK MCLK tCLKH tCLKL 1/fsn, 1/fsd LRCK1 tBCK BICK1 tBCKH tBCKL Clock Timing (TDM0 = “0”) 1/fCLK MCLK tCLKH tCLKL 1/fs LRCK1 tLRH tLRL tBCK BICK1 tBCKH tBCKL Clock Timing (TDM0 = “1”) Rev0.9...
  • Page 16 AKM CONFIDENTIAL ASAHI KASEI [AK4588] LRCK1 tBLR tLRB BICK1 tLRS tBSD SDTO1 50%TVDD tSDS tSDH SDTI Audio Interface Timing (TDM0 = “0”) LRCK1 tBLR tLRB BICK1 tBSD SDTO1 50%TVDD tSDS tSDH SDTI Audio Interface Timing (TDM0 = “1”) Rev0.9 2003/09...
  • Page 17 AKM CONFIDENTIAL ASAHI KASEI [AK4588] LRCK1 50%DVDD tMBLR 50%DVDD BICK1 tBSD 50%DVDD SDTO1 tDXS tDXH DAUX1 Audio Interface timing (Master Mode) Rev0.9 2003/09 - 17 -...
  • Page 18 AKM CONFIDENTIAL ASAHI KASEI [AK4588] SWITCHING CHARACTERISTICS (DIR/DIT part) (Ta=25°C; DVDD, AVDD4.5~5.5V, TVDD=2.7~5.5V; C =20pF) Parameter Symbol Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 External Clock Frequency fECLK 11.2896 24.576 Duty dECLK MCKO1 Output Frequency fMCK1 4.096 24.576...
  • Page 19 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Timing Diagram(DIR/DIT part) 1/fECLK tECLKH tECLKL dECLK = tECLKH x fECLK x 100 = tECLKL x fECLK x 100 1/fMCK1 MCKO1 50%DVDD tMCKH1 tMCKL1 dMCK1 = tMCKH1 x fMCK1 x 100 = tMCKL1 x fMCK1 x 100...
  • Page 20 AKM CONFIDENTIAL ASAHI KASEI [AK4588] LRCK1 50%DVDD tMBLR 50%DVDD BICK1 tBSD 50%DVDD SDTO1 tDXS tDXH DAUX1 Serial Interface Timing (Master Mode) Power Down & Reset Timing Rev0.9 2003/09 - 20 -...
  • Page 21 AKM CONFIDENTIAL ASAHI KASEI [AK4588] SWITCHING CHARACTERISTICS (ADC/DAC part and DIR/DIT part) (Ta=25°C; AVDD, DVDD, PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; C =20pF) Parameter Symbol Units Control Interface Timing (4-wire serial mode) CCLK Period tCCK CCLK Pulse Width Low tCCKL Pulse Width High tCCKH...
  • Page 22 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Timing Diagram (ADC/DAC part and DIR/DIT part) tCSS tCCK tCCKL tCCKH CCLK tCDH tCDS CDTI Hi-Z CDTO WRITE/READ Command Input Timing in 4-wire serial mode The ADC/DAC part doesn’t support READ command. tCSW tCSH CCLK...
  • Page 23 AKM CONFIDENTIAL ASAHI KASEI [AK4588] tCSW tCSH CCLK CDTI tCCZ CDTO 50%DVDD READ Data Input Timing 2 in 4-wire serial mode The ADC/DAC part doesn’t support READ command. tLOW tHIGH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop C Bus mode Timing The ADC/DAC part doesn’t support READ command.
  • Page 24 If the external clocks are not present, the AK4588 should be in the power-down mode (PDN pin = “L”) or in the reset mode (RSTN bit = “0”). After exiting reset at power-up etc., the AK4588 is in the power-down mode until MCLK and LRCK are input.
  • Page 25 Table 7. System Clock Example (Auto Setting Mode) De-emphasis Filter The AK4588 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz).
  • Page 26 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Master mode and Slave mode Master Mode can be selected by setting MASTER pin to “H”. LRCK1 and BICK1 will be outputs in Master Mode. And, Slave Mode can be selected by setting this pin to “L”. LRCK1 and BICK1 will be inputs in Slave Mode.
  • Page 27 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Mode MASTER TDM 1 TDM0 DIF1 DIF0 SDTO1 SDTI1 LRCK1 BICK1 24bit, Left 20bit, Right ↑ 256fs justified justified 24bit, Left 24bit, Right ↑ 256fs justified justified 24bit, Left 24bit, Left ↑ 256fs justified justified ↓...
  • Page 28 AKM CONFIDENTIAL ASAHI KASEI [AK4588] LRCK1 BICK1(64fs) SDTO1(o) 12 11 10 23 22 12 11 10 SDTI(i) Don’t Care Don’t Care SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0,4 Timing LRCK1 BICK1(64fs) SDTO1(o) 16 15 14...
  • Page 29 AKM CONFIDENTIAL ASAHI KASEI [AK4588] 256 B ICK LRCK1 (m ode 8) LRCK1 (m ode 12) BICK1(256fs) SDTO1(o) 32 B ICK 32 B ICK SDT I1(i) 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK...
  • Page 30 AKM CONFIDENTIAL ASAHI KASEI [AK4588] 128 B ICK LRCK1 (m ode 16) LRCK1 (m ode 20) BICK1(128fs) SDTO1(o) 32 B ICK 32 B ICK SDT I1(i) 32 B ICK 32 B ICK 32 B ICK 32 B ICK SDT I2(i)
  • Page 31 AKM CONFIDENTIAL ASAHI KASEI [AK4588] 128 B ICK LRCK1 (m ode 19) LRCK1 (m ode 23) BICK1(128fs) SDTO1(o) 32 B ICK 32 B ICK SDT I1(i) 32 B ICK 32 B ICK 32 B ICK 32 B ICK SDT I2(i)
  • Page 32 Zero Detection The AK4588 has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L” (Table 13). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2 channels.
  • Page 33 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Digital Attenuator AK4588 has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 15). ATT7-0 Attenuation Level Default -0.5dB -1.0dB -62.5dB -63dB MUTE (-∞) MUTE (-∞)
  • Page 34 System Reset The AK4588 should be reset once by bringing PDN pin = “L” upon power-up. The AK4588 is powered up and the internal timing starts clocking by LRCK1 “↑” after exiting reset and power down state by MCLK. The AK4588 is in the power-down mode until MCLK and LRCK1 are input.
  • Page 35 Power ON/OFF Sequence The ADC and DACs of AK4588 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “L”.
  • Page 36 (6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN. (7) When the external clocks (MCLK, BICK1 and LRCK1) are stopped, the AK4588 should be in the power-down mode.
  • Page 37 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Reset Function When RSTN bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go to VCOM voltage, DZF1-2 pins go to “H” and SDTO1 pin goes to “L”. Because some click noise occurs, the analog output should muted externally if the click noise influences system application.
  • Page 38 DAC partial Power-Down Function All DACs of AK4588 can be powered-down individually by PD1-4 bits. The analog part of DAC is in power-down by PD1-4 bits =”1”, however, the digital part is not in power-down by it. Even if all DACs were set in power-down by the partial power-down bits, the digital part continue to function.
  • Page 39 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Register Map Addr Register Name Control 1 TDM1 TDM0 DIF1 DIF0 SMUTE Control 2 CKS1 DFS1 LOOP1 LOOP0 SDOS DFS0 ACKS CKS0 LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ROUT1 Volume Control...
  • Page 40 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Register Definitions Addr Register Name Control 1 TDM1 TDM0 DIF1 DIF0 SMUT Default SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted DIF1-0: Audio Data Interface Modes (see Table 10) Initial: “10”, mode 2...
  • Page 41 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Addr Register Name Control 2 CKS1 DFS1 LOOP1 LOOP0 SDOS DFS0 ACKS CKS0 Default ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 bits are ignored.
  • Page 42 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Addr Register Name LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1...
  • Page 43 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Addr Register Name ATT speed ATS1 ATS0 RSTN & Power Down Control Default RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation ATS1-0: Digital attenuator transition time setting (see Table 16.) Initial: “00”, mode 0...
  • Page 44 192kHz Clock Recovery On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4588 has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel status, AK4588 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz).
  • Page 45 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Clock Source The following circuits are available to feed the clock to XTI pin of AK4588. 1) X’tal 25kΩ AK4588 Figure 17. X’tal mode Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock...
  • Page 46 AKM CONFIDENTIAL [AK4588] Sampling Frequency and Pre-emphasis Detection The AK4588 has two methods for detecting the sampling frequency as follows. 1. Clock comparison between recovered clock and X’tal oscillator 2. Sampling frequency information on channel status Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits.
  • Page 47 The AK4588 goes this mode at default. Therefore, in Parallel Mode, the AK4588 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU bit is “0”. The internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis Mode is OFF.
  • Page 48 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Biphase Input and Through Output Eight receiver inputs (RX0-7) are available in Serial Control Mode. Each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mV or more. IPS2-0 bits selects the receiver channel. When BCU bit = “1”, the Block start signal, C bit and U bit can output from each pins.
  • Page 49 CT39-CT0 bits in control registers. When bit0= “0”(consumer mode), bit20-23 (Audio channel) could not be controlled directly but be controlled by CT20 bit. When the CT20 bit is “1”, AK4588 outputs “1000” as C20-23 for left channel and output “0100” at C20-23 for right channel automatically. When CT20 bit is “0”, AK4588 outputs “0000”...
  • Page 50 RX2-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”. The AK4588 includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure 25 is a transformer of 1:1.
  • Page 51 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Q-subcode buffers The AK4588 has Q-subcode buffer for CD application. The AK4588 takes Q-subcode into registers by following conditions. 1. The sync word (S0,S1) is constructed at least 16 “0”s. 2. The start bit is “1”.
  • Page 52 Each INT0/1 pins can mask those eight events individually. Once PAR, QINT and CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4588 loses lock, registers regarding C-bit or U-bits are not initialized and keep previous value.
  • Page 53 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Error (Error) (UNLOCK, PAR,..) INT0 pin Hold Time (max: 4096/fs) INT1 pin Hold Time = 0 Register Hold ”1” Reset (PAR,CINT,QINT) Register (others) Command READ 06H MCKO,BICK2,LRCK2 (UNLOCK) Free Run (fs: around 20kHz) MCKO,BICK2,LRCK2 (except UNLOCK)
  • Page 54 ASAHI KASEI AKM CONFIDENTIAL [AK4588] PD pin ="L" to "H" Initialize Read 06H INT0/1 pin ="H" Release Mute DAC output Muting Read 06H (Each Error Handling) Read 06H (Resets registers) INT0/1 pin ="H" Figure 30. Error Handling Sequence Example 1 Rev0.9...
  • Page 55 ASAHI KASEI AKM CONFIDENTIAL [AK4588] PD pin ="L" to "H" Initialize Read 06H INT1 pin ="H" Read 06H Detect QSUB= “1” (Read Q-buffer) New data QCRC = “0” is invalid INT1 pin ="L" New data is valid Figure 31. Error Handling Sequence Example 2 (for Q/CINT) Rev0.9...
  • Page 56 When using Master mode, BICK2 and KRCK2 output pins become Hi-Z in PDN pin = ”L” and from PDN pin = ”H” till Master mode. When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4588 continues to output the last normal sub-frame data from SDTO2 repeatedly until the error is removed. When the Unlock Error occurs, AK4588 output “0”...
  • Page 57 ASAHI KASEI AKM CONFIDENTIAL [AK4588] LRCK2 BICK2 (0:64fs) SDTO2 15:MSB, 0:LSB Lch Data Rch Data Figure 33. Mode 0 Timing LRCK2 BICK2 (0:64fs) SDTO2 23:MSB, 0:LSB Lch Data Rch Data Figure 34. Mode 3 Timing LRCK2 BICK2 (64fs) 23 22...
  • Page 58 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Register Map Addr Register Name CLK & Power Down Control CS12 OCKS1 OCKS0 RSTN Format & De-em Control MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0 Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02...
  • Page 59 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Register Definitions Reset & Initialize Addr Register Name 00H CLK & Power Down Control CS12 OCKS1 OCKS0 RSTN Default RSTN: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation PWN: Power Down...
  • Page 60 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Input/Output Control Addr Register Name 02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 Default OPS02-00: Output Through Data Select for TX0 pin OPS12-10: Output Through Data Select for TX1 pin TX0E: TX0 Output Enable 0: Disable.
  • Page 61 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Mask Control for INT0 Addr Register Name 04H INT0 MASK MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0 Default MPR0: Mask Enable for PAR bit MAN0: Mask Enable for AUDN bit MPE0: Mask Enable for PEM bit...
  • Page 62 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Receiver Status 0 Addr Register Name 06H Receiver status 0 QINT AUTO CINT UNLCK DTSCD AUDION Default PAR: Parity Error or Biphase Error Status 0:No Error 1:Error It is “1” if Parity Error or Biphase Error is detected in the sub-frame.
  • Page 63 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Receiver Channel Status Addr Register Name 08H RX Channel Status Byte 0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19...
  • Page 64 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Q-subcode Buffer Addr Register Name 16H Q-subcode Address / Control 17H Q-subcode Track 18H Q-subcode Index 19H Q-subcode Minute 1AH Q-subcode Second 1BH Q-subcode Frame 1CH Q-subcode Zero 1DH Q-subcode ABS Minute 1EH Q-subcode ABS Second...
  • Page 65 ASAHI KASEI AKM CONFIDENTIAL [AK4588] Burst Preambles in non-PCM Bitstreams sub-frame of IEC958 11 12 27 28 29 30 31 preamble Aux. MSB V U C P 16 bits of bitstream Pa Pb Pc Pd Burst_payload stuffing repetition time of the burst Figure 37.
  • Page 66 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Bits of Pc Value Contents Repetition time of burst in IEC60958 frames data type ≤4096 NULL data Dolby AC-3 data 1536 reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension...
  • Page 67 AKM CONFIDENTIAL ASAHI KASEI [AK4588] Non-PCM Bitstream timing 1) When Non-PCM preamble is not coming within 4096 frames, PDN pin Bit stream Repetition time >4096 frames AUTO bit Pc Register “0” Pd Register “0” Figure 38. Timing example 1 2) When Non-PCM bitstream stops (when MULK0=0),...
  • Page 68 CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4588 should be reset by PDN pin = “L”. Register of ADC/DAC part can not read. 10 11 12 13 14 15...

  • Page 69: Start Condition

    All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4588 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE).
  • Page 70 In the read mode, the slave, the AK4588 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data.
  • Page 71 After receipt the start condition and the first byte, the AK4588 generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of AK4588. The format is MSB first, and those most significant 3-bits are “Don’t care”.

  • Page 72: Random Read

    After receipt of the slave address with R/W bit set to “1”, the AK4588 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does...

  • Page 73: System Design

    - Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance. - In case of coaxial input, ground of RCA connector and terminator should be connected to PVSS of the AK4588 Rev0.9...
  • Page 74 AKM CONFIDENTIAL ASAHI KASEI [AK4588] with low impedance on PC board. Rev0.9 2003/09 - 74 -...
  • Page 75 System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4588 as possible, with the small value ceramic capacitor being the nearest.
  • Page 76 AKM CONFIDENTIAL ASAHI KASEI [AK4588] PACKAGE 80-pin LQFP ( Unit : mm ) 14.0±0.2 12.0±0.2 0° ~ 10° 0.20±0.1 0.50 0.08 1.25TYP 0.50±0.1 0.10 Material & Lead finish Package: Epoxy Lead-frame: Copper Lead-finish Soldering (Pb free) plate Rev0.9 2003/09 - 76 -...

  • Page 77: Important Notice

    • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content...
  • Page 78 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.