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When FF-TF is triggered,
test point S goes high.
Transistor V45 therewith
becomes
conducting
and gates
out the signal V42 via diode D45,
Consequently,
PI
cannot
trigger
FF-TF again
before the punching
cycle
is completed,
i.e.
when
test
point
S goes low,
Capa-
citor C35 located
between
the base and collector of
V42, prevents
signals
having a duration
of less than
about
10us from starting
a punching
cycle.
When
the
collector
of V45 goes low, the register
inputs are
opened
and the character
that
is to be punched
is en-
tered
into the register.
Register
flip-flops
that
are I-set receive
holding current
via feedback
re-
sistors
R10 - R18, O-setting takes
place when V45
is cut off.
Signal TF also triggers
timing
flip-flop
FF-Al
which,
in turn,
triggers
timing
flip-flop
FF-A2.
The pur-
pose of these
flip-flops
is to keep signal
PR low
for 13.3ms,
thus limiting the punching speed to 75
characters
per second.
The signal
from the timing
flip-flops
proceeds
via
OR circuit
IC201
and a 200ns delay circuit
to tran-
sistor V43. V43 becomes
conducting
and gates out
data signals via diodes
Dl] - D9, Simultaneously,
the gate used
for the PI signal
is closed
via diode
D46, and transistor
V38 becomes
conducting.
The PR
signal
goes
low and remains
low during
the entire
punching
cycle.
During time TF (and TP) the stepper motor steps
one step.
See section
4.3.3.
When
flip-flop
FF-TF returns
to the 0 state,
flip-
flop FF-TP
is triggered.
The TP signal
(0 vj cuts
off transistor V40, wherewith
diodes
D28 - D36 are
blocked
and the information
in the register
is gated
to the punch solenoids.
When
FF-TP returns
to the
O state,
V45 is cut off, wherewith
the register
is
O-set.
When FF-A2 returns
to the 0 state,
V43 is
cut off, wherewith
signal
PR goes
high,
thus indi-
cating
externally that the punch is ready to re-
ceive
and punch a new
character.
The punching
cycle comprises
two phases:
feed and
recording.
See Fig.4 . Feed takes
place during time
TF (approx 10.5ms);
recording
takes
place during
time TP (approx 1.85ms).
Power is supplied
to the
stepper motor during the entire
punching
cycle TF+
TP. The motor thus keeps the tape stationary while
it is punched.
7Ous after the data is entered
into
the buffer
register,
signal
PR goes
low and remains
low until the character
has been punched.
If PR is high the punching cycle is started when PI
goes high.
See appendix
1. (PI is blocked
at V12
when PR is low), The inverted
PI pulse at VI1
is
delayed
10us at IC15/12 because
of R65, C13.
The
delayed PI pulse triggers FFPC, setting IC12/6 high
wherewith
the reset
condition
at the buffer
regis-
ter
flip-flops
FFB1-9
vanishes.
At the same
time
FFTS
is triggered
and
]-set.
The high condition
on
the Q-output of FFTS opens
the data
inputs at V1-V9
via ICII/1
(IC11/2 is high at no manual
feed). FFTS
is l-set 60us (C35). At the trailing edge of the
flops
FFB]
- FFB9
are O-set).
The TP signal
is
also available
at connector
Pl (for external
stro-
bing).
When
FFTPQ
is low the stepper
motor
drive
circuits
still receive current,
via IC13/4,
as
described
above.
This
causes
the tape to stand
still
during punching.
FFSLQ retains
PR low via IC19/10,
D10 and v13,
causing the cycle time to be 13.33ms.
This results
in maintained
speed at 75ch/s.
When
FFTP returns
to its O-state
the punch solenoid
and the stepper motor
drive
circuits
are switched
off.
When the SL pulse goes
high,
the FFPC is reset
wherewith
the buffer
register
is cleared.
At the
same
time the PR signal
goes
high indicating
exter-
nally that the punch is ready to receive
and punch
a new
character.
Following
description
refers
to Figs.
5 and 6 which
describe
the new and old versions
respectively,
Gu.
within
brackets
concern
the old version
DTL).
The stepper
motor
windings
receive
signals
from
2-bits counter IC8 (IC2) FFC] and FFC2 (FF~C1 and
FF-C2).
These
signals
are
decoded
in gating
sys-
tem IC7 (1C1/6,
IC4/1
and IC4/11).
The signals
are
gated
out
during
times
TF + TP.
sD
—
7
STEPPER
MOTOR
COUNTER
:
f
[
Fon ond
winding
motor
shut
off
during back spac2ja t]b
Sic 4d
ing
&D
La
9
TS clock
TF 4 TP
pac
Current switch
Ley
Stepper motor
FIG 5
Flip-flops FFC]
(FF-Cl) and FFC2 (FF-C2) are JK flip-
flops.
The counter
is triggered
by the trailing
(leading)
edge of signal
TS (TF).
It can
count
to 3,
either
up or down,
depending
on the polarity
of con-
dition
SD,
For
forward
feed,
the counter
assumes
sta-
tes 10, O1, 00, 10 etc. As a result,
the winding
in
the stepper
motor
are
energized
in ascending
sequence
Lil, L12, L10 ete.
For backspacing,
the counter
assu-
mes states
OT, 10, 00, O1 etc.
Consequently,
the win-
dings are energized
in descending
sequence
L12, L11,
L10 ete.
See tables
in sections
4.3.3.1
and 4.3.3.2
respectively.
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