DEC DECtape 551 Manual page 30

The next circuit action depends on whether an initial time delay is selected. If no delay is
selected, the UT CONO SET LONG pulse, applied to a capacitor-diode gate enabled by
NOT UT TIME, sets up the RW RQ state. Otherwise, the transition of UT 5T ART going to 0
at the end of the delay period sets up the RW RQ state. In the RW RQ state, the DECtape con- ,
trol waits for the proper marks to be read from the mark track before transmitting data. In the
case of write block marks, the control waits for a
1
to shift into TBM3.
At TP2 time just before the first bits of the block mark must be written out, a
1
shifts into
TMB3. The resulting transition, applied to a capacitor-diode gate at
1
B7 sets up the RW
ACTIVE state.
Once in the active state, a host of actions is enabled. The first action occurs in drawing TMT.
The TCT fl ip-flop controls the separation of each 6-bit character from the data control into two
3-bit bytes. The capacitor-diode gate AND circuits at the complement input to this flip-flop
ensure that it returns to the 0 state when data transmission is not active. The RW ACTIVE level
begins too late to complement TCT on the sam@hat shifted the
1
into TBM3 because of the
delay of the capacitor-diode gates.
A NAND gate in the lower left of drawing RWBC produces the RW ODD signal when RW ACTIVE
and TCT(O) are both present. RW ODD enables a capacitor-diode gate which triggers the RW
CLEAR pulse a(!fj/in preparation for accepting the block mark data.
RW. ODD also enables the logic at the upper right of drawing RWBC to produce a RWB ( )
DC pulse on the
next~
The TDATA register is cleared (see Data Write Operations) and the
command is not UT WRTMi therefore, a pulse is produced each TP4. At this point in the logic,
the direction of tape motion makes a difference. If the direction is reverse, the
~~!!lplement
_
...
"
...
""',.,.
...........
obverse of the gata must be formed so that reading back in the forward direction requires no
data manipulation. The op.x.erse is fO,rmed by commanding the data control to sh!ft rigbt instead
of left and by accepting bytes from the right end of the data accumulator instead of the left
end. The complement is formed in the write buffer logic as explained below. Therefore, the
RWB
~~
DC pulse triggers either (LT) RWB
+-(-..,.)
DC(l) FWD or (RT) RWB
~(-~)
DC(l)
REV depending on whether the tape motion is forward or reverse respectively.
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