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3) PIN Function table
Pin
Name
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A0~A10/AP
Address
BA
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input / Output Mask
DQ0~15
Data Input / Output
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
N.C/RFU
No Connection/
Reserved for Future Use
I IC504 BA5810FM
28
27
26
+
—
LOADING PRE
FWE REV
X3
1
2
3
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least one cycle prior to new command. Disable input
buffers for power down in standby.
Row/Column addresses are multiplexed on the same pins. Row address:
RA0~RA10, column address: CA0~CA7
Selects bank to be activated during row address latch time. Selects bank for
read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS
low. Enables column access.
Enables write operation and row precharge. Latches data in starting from
CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks
data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This is recommended to be left No Connection on the
device.
23
22
25
24
+
—
7.5k
16k
7.5k
16k
POWER
PREVCC
SAVE
(PRE. LODING)
4
5
6
7
21
20
CD1~
CB4
POWVCC34
MUTE
(CH3, CH4)
7.5k
16k
7.5k
16k
PREVCC12
(CH1. CH2)
8
9
- 2-23 -
19
18
17
16
10k
10k
10k
10k
10k
10k
+
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
LEVEL
SHIFT
10k
10k
10k
10k
10
11
12
13
15
10k
10k
SHIFT
10k
10k
14
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