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13255
4K UV
PROM Module
13255-91007/07
Rev
AUG-01-76
3.4
3.4.1
3.5
3.5.1
3.5.2
3.6
3.6.1
ACCESS CONTROL.
This block selects the specific PROM to be accessed, enables the
appropriate portion of the data path and determines when the
processor reads the data from the terminal bus.
When WR[TE and
1/0
are high, i.e. a read from memory is desired,
and REQ Is low, then U210, pin 8 is high.
If BLOCK A is high,
then u17, pin 11 is low and ENABLE A is high1 similarly, if BLOCK B
is high, then 1117,
pin
3 is low and ENABLE B is high.
The signal
EN~BLE
A enables decoder U15 and ENARLE B enables decoder Ul11.
ADDR8-10 are decoded to determine the appropriate Chip select as
shown below:
AODRIO
AOOR9
ADORa
PROM ENABLED
~--~--------~--~------~--~~-------~--
0
0
0
At,
81
0
0
1
A2,
62
0
1
0
A3, B3
0
1
t
A4, B4
1
0
0
AS,
65
1
0
1
A6, 86
1
1
0
A7, B7
1
1
1
A8, B8
If either ENABLE A or ENABLE B is high, then the sIgnal PROM SELECT
1s high also.
DATA PATH.
This block allOWS data from the PROMs to be routed onto the terminal
bus.
If ENABLE A is high, then
U25
and
U35
are enabled, allowing data
from A1-A8 to apPear on the terminal bUS in ground true form.
If ENABLE B is high, then U211 and U311 are enabled, allowing data
from 81-B8 to appear on the terminal bus in ground true form.
TIMING.
This blOCK determines the time at Which the processor is allowed
to read the data on the terminal bus.
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