Communications Processor (Comm) - Memorex 7300 Manual

Communications Processor (COMM)
The integrated communications adapter (ICA) in the
Comm processor, Figure 1-11, consists of four Common
Control PC boards that provide the interface between
individual communication-line adapters and the processing
unit. The 1/0 registers for state 0 are contained on these
Common Control boards. The two Bead registers are
combined in dual-input multiplexer IC's, as shown in
Table 1-2 of the Register File discussion. Write Address
and Write Data are each discrete regist1m. In addition to
the functions implied in Figure 1-11, the common control
boards perform the recognition of certain message-framing
control characters during the receipt of both synchronous
and asynchronous transmissions.
Each communication line requires a Line Adapter (LA)
and a Signal Conditioner (SC). The latter converts internal
logic signals to those required by external equipment; this
SC may be a level translator, used for local terminals and
external modems, or it may be an internal modem.
Present internal modems are the MRX 1220
(asynchronous mode only), equivalent to a Western
Electric* 103A data set, and the MRX 1222 (synchronous
or asynchronous modes), equivalent to a Western Electric
202C.
The Line Adapter comprises an Outbound Buffer and an
Inbound Multiplexer, housed on separate PC boards.
*Tradename of American Telephone and Tele1graph Corp.
Five combinations of Line Adapters are available:
• Asynchronous eight-level
• Synchronous EBCDIC, basic
• Synchronous ASC 11, basic
• Synchronous EBCDIC, code transparent
• Synchronous ASCII, code transparent
Some logic for the code transparent modes is contained
on a special Signal Conditioner board. This means that
code transparent transmissions must use an external
modem. With this limitation, the Line Adapters are
interchangeable (that is, the 2-board LA sets are plug
compatible), as are the Signal Conditioners.
A direct data path is provided between the Outbound
Buffer and the Input Multiplexer for diagnostic testing.
During such tests, data from the Write registers is sent to
the Signal Conditioner, but is also routed through the
Input Multiplexer to the 16-character queue, and thence
to the Read registers. This "Loop Test" mode may be
applied selectively to any Line Adapter, permitting
diagnostic testing of the selected line without disturbing
the normal transmit-receive capability of the other lines.
r - - - - - - - - - - - - - - - - - ,
s
H
A
R
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D
R
E
s
0
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WRITE
INTEGRATED COMMUNICATIONS
I
ADDR
ADAPTER (ICA)
REG
GROUP Ill
EXT. REGS,
PROCESSOR
STATE 0
READ
ADDR
REG
LINE
ADDRESS
SELECTION
BLOCK CHECK
CONTROL
CHARACTER
DECODE
OUTBOUND DATA BUS
BCC CONTROL BUS
SIGNAL
CONDITIONER
--~-1
(1OF16)
READ
DATA
REG
H---...a..----..........111------..._-IN-B-OU_N_D_D_A_T_A_B_US--------------·
I
L----------E2~~2r!.£Q.~!!Q.L_
______
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Figure
1-11.
Communications Processor
1-15