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4-2.
OSCILLATOR CIRCUIT
The clock (1C604-1) is generated by attaching crystal oscillator (23 MHz) to I1C604 outside. This clock is matched the
phase at rising down of H-SYNC when fetching the video signal. At that time, the clock signal is disordered. It is corrected
at the circuit (IC601, IC605) to reduce the noise. Memory control and etc. are performed by this clock (IC601 pin 25) as
master clock. This signal is also used as sampling clock of A/D converter. Furthermore, this signal is delayed the phase
for high scan by using the delay IC (IC605). 46MHz sampling is performed by shifting the phase of two A/D converters
(IC7, 8) parallel.
Oscillator Circuit
H-SYNC
(IC601-@)
CXD 8726R
SCLK
(SAMPLING CLOCK)
X601
(23 MHz)
H-SYNC
SCLK
(usual)
SCLK
(when fetching)
ww)
WY
Phase matching
Phase matching
4-3.
1C601 PERIPHERAL CIRCUIT
IC601 consists of following blocks.
(1) Register for serial data storing from system control (IC505)
@) Various mode setting
22 byte
@ SYNC signal processing parameter
-———— 4 byte
@ Coefficient for scaling calculation
————
128 byte
(@) Gamma data
——
34 byte
(2) Frame memory write and read control
(3) Thermal head control
(4) SYNC signal processing circuit
(5) 1 line memory (for print)
(6) Image scaling calculation circuit
Each block operation is decided by serial data from system control (IC505) and mode switching terminal.
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