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The Cypress CYW20734 is a Bluetooth 4.1-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver.
Manufactured using the industry's most advanced 40 nm CMOS low-power process, the CYW20734 employs the highest level of
integration to eliminate all critical external components, thereby minimizing the device's footprint and the costs associated with
implementing Bluetooth solutions.
The CYW20734 is the optimal solution for applications in wireless input devices including game controllers, remote, keyboards, and
joysticks. Built-in firmware adheres to the Bluetooth Low Energy (BLE) profile and the BLE Human Interface Device (HID) profile.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
BCM20734
BCM20734UA1KFFB3G
Applications
Game controllers
■
Wireless pointing devices (mice)
■
Remote controls
■
Wireless keyboards
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Joysticks
■
Home automation
■
Point-of-sale input devices
■
3D glasses
■
Blood pressure monitors
■
"Find me" devices
■
Heart rate monitors
■
Proximity sensors
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Thermometers
■
Cypress Semiconductor Corporation
Document Number: 002-14874 Rev. *S
Single-Chip Bluetooth Transceiver for
CYW20734
CYW20734UA1KFFB3G
Features
Complies with Bluetooth Core Specification version 4.1
■
including BR/EDR/BLE
BLE HID profile version 1.00 compliant
■
Bluetooth Device ID profile version 1.3 compliant
■
Supports Generic Access Profile (GAP)
■
Supports Adaptive Frequency Hopping (AFH)
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Excellent receiver sensitivity
■
Programmable output power control
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Integrated ARM Cortex-M3 microprocessor core
■
On-chip power-on reset (POR)
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Support for EEPROM and serial flash interfaces
■
Integrated low dropout regulator (LDO)
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On-chip software controlled power management unit
■
Programmable key scan matrix interface, up to 8 × 20 key-
■
scanning matrix
Three-axis quadrature signal decoder
■
PCM/I
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Infrared modulator
■
IR learning
■
Auxiliary ADC with up to 28 analog channels
■
One mono microphone input
■
On-chip support for serial peripheral interface (master and
■
slave modes)
Broadcom Serial Communications interface (compatible with
■
NXP I
Package type:
■
❐
❐
•
198 Champion Court
Wireless Input Devices
Cypress Part Number
2
S Interface
2
C slaves)
90-pin FBGA package (8.5 mm × 8.5 mm)
RoHS compliant
,
•
San Jose
CA 95134-1709
Revised Tuesday, October 4, 2016
CYW20734
•
408-943-2600
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Table of Contents
Related Manuals for Cypress CYW20734
Summary of Contents for Cypress CYW20734
- Page 1 Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.
- Page 2 IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates.
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Page 3: Table Of Contents
CYW20734 Contents 1. Functional Description ..........4 1.15 Serial Peripheral Interface ......... 15 1.1 Bluetooth Baseband Core ........4 1.16 Infrared Modulator ..........15 1.2 Microprocessor Unit ..........5 1.17 Infrared Learning ..........16 1.3 Integrated Radio Transceiver ........ 6 1.18 Power Management Unit........ -
Page 4: Functional Description
(HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF) enhancements. 1.1.2 Bluetooth 4.1 Features The CYW20734 supports the following Bluetooth v4.1 features. Secure connections (BR/EDR) ■ Fast advertising interval ■... -
Page 5: Microprocessor Unit
❐ 1.1.4 Test Mode Support The CYW20734 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. -
Page 6: Integrated Radio Transceiver
1.2.2 External Reset An external active-low reset signal, RESET_N, can be used to put the CYW20734 in the reset state. An external voltage detector reset IC with 50 ms delay is needed on the RESET_N. The RESET_N should be released only after the VDDO supply voltage level has been stabilized for 50 ms. - Page 7 1.3.7 Receiver Signal Strength Indicator The radio portion of the CYW20734 provides a receiver signal strength indicator (RSSI) signal to the baseband, so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power.
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Page 8: Peripheral Transport Unit
The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps. The baud rate of the CYW20734 UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. - Page 9 HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW20734 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±2.5%. This should include all temperature, voltage, and process variation dependent offsets.
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Page 10: Pcm Interface
The CYW20734 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW20734 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. - Page 11 1.6.2 HID Peripheral Block The peripheral blocks of the CYW20734 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.
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Page 12: Gpio Ports
1.7 GPIO Ports The CYW20734 has 40 general-purpose I/Os (GPIOs) in a 90-pin package. All GPIOs support programmable pull-ups and are capable of driving up to 8 mA at 3.3V or 4 mA at 1.8V, except P26, P27, P28, and P29, which are capable of driving up to 16 mA at 3.3V or 8 mA at 1.8V. -
Page 13: Mouse Quadrature Signal Decoder
1.11 Microphone Input The CYW20734 integrates support for a differential or single-ended mono microphone. This reduces the requirement on external components because there is no need for a separate microphone amplifier. The microphone input has a user-programmable gain range of 0–42 dB with 3 dB steps. A microphone bias output from the chip is provided that can be used to bias an electret condenser- type microphone. -
Page 14: Pwm
CYW20734 1.12 PWM The CYW20734 has four internal PWMs. The PWM module consists of the following: PWM1–4 ■ Each of the four PWM channels, PWM1–4, contains the following registers: ■ 10-bit initial value register (read/write) ❐ 10-bit toggle register (read/write) ❐... -
Page 15: Shutter Control For 3D Glasses
CYW20734 has optional I/O ports that can be configured individually and separately for each functional pin. The CYW20734 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20734 can also act as an SPI slave device that supports a 1.8V or 3.3V SPI master. -
Page 16: Infrared Learning
The CYW20734 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals. For modulated signals, the CYW20734 can detect carrier frequencies between 10 kHz and 500 kHz, and the duration that the signal is present or absent. The CYW20734 firmware driver supports further analysis and compression of the learned signal. The learned... -
Page 17: Pin Assignments
CYW20734 2. Pin Assignments 2.1 Pin Descriptions Table 7. Pin Descriptions Pin Number Pin Name Power Domain Description Radio I/O RFOP PAVDD RF antenna port RF Power Supplies IFVDD1P2 IFVDD1P2 IFPLL power supply LNAVDD1P2 LNAVDD1P2 RF front-end supply VCOVDD1P2 VCOVDD1P2... - Page 18 CYW20734 Table 7. Pin Descriptions (Cont.) Pin Number Pin Name Power Domain Description PCM_IN I, PU VDDO Data input for PCM interface. Alternate function: S data input PCM_OUT O, PD VDDO Data output for PCM interface. Alternate function: S data output...
- Page 19 CYW20734 Table 8. GPIO Pin Descriptions Default Di- Post-Reset Power Do- Alternate Function Description Number Name rection State State main Input Floating Floating VDDO GPIO: P0 ■ Keyboard scan input (row): KSI0 ■ A/D converter input 29 ■ Peripheral UART: puart_tx ■...
- Page 20 CYW20734 Table 8. GPIO Pin Descriptions (Cont.) Default Di- Post-Reset Power Do- Alternate Function Description Number Name rection State State main Input Floating Floating VDDO GPIO: P6 ■ Keyboard scan input (row): KSI6 ■ Quadrature: QDZ0 ■ Peripheral UART: puart_rts ■...
- Page 21 CYW20734 Table 8. GPIO Pin Descriptions (Cont.) Default Di- Post-Reset Power Do- Alternate Function Description Number Name rection State State main Input Floating Input enable, VDDO GPIO: P14 ■ pull-down Keyboard scan output (column): KSO6 ■ A/D converter input 21 ■...
- Page 22 CYW20734 Table 8. GPIO Pin Descriptions (Cont.) Default Di- Post-Reset Power Do- Alternate Function Description Number Name rection State State main Input Floating Floating VDDO GPIO: P24 ■ Keyboard scan output (column): KSO16 ■ SPI_1: SPI_CLK (master and slave) ■...
- Page 23 CYW20734 Table 8. GPIO Pin Descriptions (Cont.) Default Di- Post-Reset Power Do- Alternate Function Description Number Name rection State State main Input Floating Floating VDDO GPIO: P32 ■ A/D converter input 7 ■ Quadrature: QDX0 ■ SPI_1: SPI_CS (slave only) ■...
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Page 24: Ball Map
During power-on reset, all inputs are disabled. b. The post-reset state is the GPIO state just after a power-on reset before firmware gets loaded. 2.2 Ball Map The CYW20734 ball map is shown in Figure Figure 8. CYW20734 Ball Map... -
Page 25: Specifications
CYW20734 3. Specifications 3.1 Electrical Characteristics Table 9 shows the maximum electrical rating for voltages referenced to VDD pin. Table 9. Absolute Maximum Voltages Specification Requirement Parameter Unit Minimum Nominal Maximum Ambient Temperature of Operation –30 °C Storage temperature –40 –... - Page 26 CYW20734 Table 11 shows the digital level characteristics for (VSS = 0V). Table 11. VDDC LDO Electrical Specifications Parameter Conditions Min. Typical Max. Unit Input Voltage – 1.62 Nominal Output – – Voltage DC Accuracy Accuracy at any step, including bandgap reference. –5 – Output Voltage Range 0.89 –...
- Page 27 CYW20734 Table 12. ADC Microphone Specifications Parameter Symbol Conditions/Comments Min. Typical Max. Unit Analog supply voltage AVBAT Battery and I/O supply 1.62 Analog core supply AVDDC ±10% 1.08 1.32 Audio supply Mic_avdd Only available for audio applications when audio supply is separated from...
- Page 28 CYW20734 Table 12. ADC Microphone Specifications (Cont.) Parameter Symbol Conditions/Comments Min. Typical Max. Unit MIC bias noise – PGA input referred. 6 dB attenuation – – µV ■ is assumed from MIC bias output to PGA input. 20 Hz to 8 kHz ■...
- Page 29 CYW20734 Table 14. Bluetooth and BLE Current Consumption, Class 1 Operating Mode Typical Unit DM1/DH1 32.15 DM3/DH3 38.14 DM5/DH5 38.46 3DH5/3DH5 37.10 Page scan μA Sniff slave (495 ms) μA Sniff slave (22.5 ms) Sniff slave (11.25 ms) 4.95 HIDOFF (deep sleep) 2.69...
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Page 30: Rf Specifications
CYW20734 3.2 RF Specifications Note: All specifications in Table 16 are for industrial temperatures. ■ All specifications in Table 16 are single-ended. Unused inputs are left open. ■ Table 16. Receiver RF Specifications Parameter Conditions Minimum Typical Maximum Unit General Frequency range –... - Page 31 CYW20734 Table 16. Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Out-of-Band Blocking Performance, Modulated Interferer 776–764 MHz CDMA – –10 – 824–849 MHz CDMA – –10 – 1850–1910 MHz CDMA – –23 – 824–849 MHz EDGE/GSM –...
- Page 32 CYW20734 Note: All specifications in Table 17 are for industrial temperatures. ■ All specifications in Table 17 are single-ended. Unused inputs are left open. ■ Table 17. Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit General Frequency range –...
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Page 33: Timing And Ac Characteristics
CYW20734 Table 18. BLE RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range 2402 – 2480 RX sense GFSK, 0.1% BER, 1 Mbps – –96.5 – TX power – – Mod Char: Delta F1 average Mod Char: Delta F2 max 99.9... - Page 34 CYW20734 3.3.2 SPI Timing The SPI interface can be clocked up to 24 MHz. Table 20 Figure 10 show the timing requirements when operating in SPI Mode 0 and 2. Table 20. SPI Mode 0 and 2 Reference Characteristics Minimum...
- Page 35 CYW20734 Table 21 Figure 11 show the timing requirements when operating in SPI Mode 0 and 2. Table 21. SPI Mode 1 and 3 Reference Characteristics Minimum Maximum Unit ∞ Time from slave assert SPI_INT to master assert SPI_CSN (DirectRead) ∞...
- Page 36 CYW20734 3.3.3 BSC Interface Timing The specifications in Table 22 references Figure Table 22. BSC Interface Timing Specifications (up to 1 MHz) Reference Characteristics Minimum Maximum Unit Clock frequency – 1000 START condition setup time – START condition hold time –...
- Page 37 CYW20734 3.3.4 PCM Interface Timing Short Frame Sync, Master Mode Figure 13. PCM Timing Diagram (Short Frame Sync, Master Mode) P C M _ B C LK PC M _ SY N C P C M _ O U T H IG H IM P ED A N C E...
- Page 38 CYW20734 Short Frame Sync, Slave Mode Figure 14. PCM Timing Diagram (Short Frame Sync, Slave Mode) P C M _ B C L K P C M _ S Y N C P C M _ O U T H IG H IM P E D A N C E P C M _ IN Table 24.
- Page 39 CYW20734 Long Frame Sync, Master Mode Figure 15. PCM Timing Diagram (Long Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE Bit 0 Bit 1 Bit 0 PCM_IN Bit 1 Table 25. PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Reference Characteristics Minimum Typical...
- Page 40 CYW20734 Long Frame Sync, Slave Mode Figure 16. PCM Timing Diagram (Long Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT Bit 0 HIGH IMPEDANCE Bit 1 Bit 0 Bit 1 PCM_IN Table 26. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Reference Characteristics Minimum Typical...
- Page 41 S WS is low, and right-channel data is transmitted when I S WS is high. Data bits sent by the CYW20734 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.
- Page 42 CYW20734 Table 27. Timing for I S Transmitters and Receivers Transmitter Receiver Lower LImit Upper Limit Lower Limit Upper Limit Notes Clock Period T – – – – – – Master Mode: Clock generated by transmitter or receiver HIGH t 0.35T...
- Page 43 CYW20734 Figure 17. I S Transmitter Timing > 0.35T > 0.35T = 2.0V = 0.8V > 0 < 0.8T SD and WS T = Clock period = Minimum allowed clock period for transmitter T = T * t is only relevant for transmitters in slave mode. Figure 18. I S Receiver Timing > 0.35T > 0.35 = 2.0V = 0.8V > 0.2T > 0 SD and WS T = Clock period...
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Page 44: Mechanical Information
CYW20734 4. Mechanical Information 4.1 Package Diagram Figure 19. CYW20734 8.5 mm × 8.5 mm 90-Pin FBGA Package Document Number: 002-14874 Rev. *S Page 44 of 51... -
Page 45: Tape Reel And Packaging Specifications
Tape width 16 mm Tape pitch 12 mm The top-left corner of the CYW20734 package is situated near the sprocket holes, as shown in Figure Figure 20. Pin 1 Orientation Pin 1: Top left corner of package toward sprocket holes Document Number: 002-14874 Rev. -
Page 46: Ordering Information
CYW20734 5. Ordering Information Table 29. Ordering Information Part Number Package Ambient Operating Temperature CYW20734UA1KFFB3G 90-pin FBGA 0°C to 70°C Document Number: 002-14874 Rev. *S Page 46 of 51... - Page 47 CYW20734 A p p e n d i x A : A c r o n y m s a n d A b b r e v i a t i o n s The following list of acronyms and abbreviations may appear in this document.
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Page 48: Document History
CYW20734 Document History Document Title: CYW20734 Single-Chip Bluetooth Transceiver for Wireless Input Devices Document Number: 002-14874 Orig. of Submission Revision Description of Change Change Date 20734-DS100-R – – 10/28/13 Initial release. 20734-DS101-R Updated: • The CYW20734 is Bluetooth 4.1-compliant. The current version of the CYW20734 does not support HS. - Page 49 CYW20734 Document Title: CYW20734 Single-Chip Bluetooth Transceiver for Wireless Input Devices Document Number: 002-14874 20734-DS107-R Updated: • “External Reset” on page 14. • Table 12: “Digital I/O Characteristics,” on page 42. • Table 14: “Current Consumption For BR and EDR, Class 1,” on page 44.
- Page 50 CYW20734 Document Title: CYW20734 Single-Chip Bluetooth Transceiver for Wireless Input Devices Document Number: 002-14874 20734-DS117-R Updated: – – 03/15/16 • “Combined baud rate error of the two devices is within ±2.5%” 20734-DS118-R – – 04/25/16 Deleted: • “Supports Broadcom proprietary LE data rate up to 2 Mbps”.
- Page 51 (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
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