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GP4 Backend block diagram (LVDS Tx & Local Dimming)
Copyright © 2012 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
[LDM_CK]
[LDM_D0]
[STB_SCL]
[STB_SDA]
[LDM_VSYNC]
Main SoC
MTK
Dual-link LVDS Output
LVDS Tx
Block
Dual-link LVDS Output
L/DIMO_SCLK
L/DIMO_MOSI
I2C_SCL1
I2C_SDA1
L/DIMO_VS
PANEL_VCC
(+12V)
51Pin
LVDS
24
Output
10-bit (R)
LVDS_SEL
BIT_SEL_LOW
41Pin
LVDS
24
10-bit (R)
Output
•
LVDS_SEL : "H"=JEIDA, "L" or NC=VESA (LGD)
•
BIT_SEL : "H" or NC = 10-bit, "L" = 8-bit
LGE Internal Use Only
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