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The MC44302A is unique in that it uses the VCO loop as a
frequency reference for the tuner AFT loop. After signal
acquisition and phase lock, the VCO and AFT loops will
reach a steady state condition. The VCO will have moved
only a small amount from it's nominal frequency (∆f VCO ) with
the tuner local oscillator (∆f LO ) correcting for the majority of
the frequency error (∆f e ). Therefore in steady state condition
∆f e = ∆f VCO + ∆f LO , and ∆f LO >> ∆f VCO . This is due to the
much higher gain in the tuner LO loop when compared to that
of the VCO loop. In this way, the VCO can be used as the
frequency reference for the AFT system provided that the
PLL can be initially locked to the incoming IF signal. This
combination of the tuner LO loop and the VCO loop forms a
double loop PLL system. Analysis shows that the overall
system stability can be assured by treating the VCO loop as
a single stand alone PLL. This is valid if the VCO loop has low
gain and high bandwidth which guarantees initial capture,
while the tuner LO loop has high gain and low bandwidth
which minimizes frequency and phase offsets.
The AFT system is designed to acquire the vision carrier,
without false locking to the sound or adjacent sound carriers,
with an initial tuner LO frequency error of 2.0 MHz. This
error is reduced to less than
acquisition and after both the VCO loop and tuner AFT loop
have reached their steady state condition. In contrast, the
discriminator coil type of AFT has a highly asymmetric lock
characteristics with a frequency error in the range of about
–2.0 MHz to 1.0 MHz. This large frequency error is due to the
effects of lower loop gain combined with the IF filter slope.
Higher loop gain can be incorporated into the discriminator
coil type of AFT but circuit problems due to large dc offsets,
and IF stability due to coil radiation at the picture carrier
frequency can be difficult to resolve. In order to achieve a
high performance level, without encountering the ill effects
associated with high gain discriminator circuits, a novel
approach to establishing PLL lock up was developed.
Figures 24 and 25 graphically illustrate the Acquisition
Circuit operation. In the absence of an IF signal, the
Acquisition Circuit examines the state of the Video (I) and
Sound (Q) demodulators, detecting that the VCO is out of
lock. On loss of lock, the AFT Output at Pin 11 (tuner LO
drive) is clamped, and the Lock Detector output at Pin 18 is
placed in a sink mode, causing its filter capacitor to
discharge. As the capacitor voltage falls below 3.7 V, the
application of a VCO offset starts and is completed at 3.0 V.
The capacitor voltage will continue to fall stopping at 2.7 V
until the Acquisition Circuit detects a signal. At this point both
the tuner and IF are offset by the same amount from their
nominal frequency of 45.75 MHz. Thus a picture carrier
would now be converted to 43.75 MHz and the Main VCO
Loop voltage at Pin 19 would be centered within its dynamic
range at 3.2 V.
The AFT offset is controlled by the system designer to
approximately –2.0 MHz. This is done so that if a nominal IF
14
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MC44302A
10 kHz upon establishing
signal appeared, its picture carrier would be centered in the
IF filter passband where there is minimum attenuation. Note
that even if the tuner LO drifts by as much as 2.0 MHz, the
signal will still not be significantly attenuated.
On the arrival of a signal, beat notes are detected at the
output of the demodulators, and the Lock Detector output is
again placed in a sink mode to further discharge the filter
capacitor. When the capacitor voltage falls below 1.3 V, the
VCO Sweep is initiated at Pin 19. This causes the VCO to be
swept an additional –2.0 MHz from its out of lock nominal
centered IF frequency. During this negative sweep, the PLL
Phase Detector is inhibited so that a phase lock cannot be
obtained. When the capacitor voltage at Pin 19 falls to 2.0 V,
the Phase Detector is made active and the VCO is swept in a
positive direction from –2.0 MHz to 2.0 MHz of the out of lock
centered IF frequency. The PLL will therefore lock to the first
carrier it encounters. This in fact has to be a vision carrier
since the sound carrier is more than 2.0 MHz below the
nominal frequency, and the adjacent lower channel sound
carrier is higher than the vision carrier. PLL lock can occur at
any point during the positive going sweep of Pin 19 from
2.0 V to 4.2 V. On achieving lock, the Lock Detector output is
released allowing the voltage across the filter capacitor to
rise. When this voltage reaches 3.0 V, a gradual removal of
the VCO offset starts. At 3.7 V removal is completed, the
VCO Sweep circuit is inhibited, and the AFT clamp is
removed. The phase detector remains permanently enabled.
Upon removal of the AFT Clamp, the error voltage that
appears at the AFT Amplifier output will drive the incoming
signal towards the nominal IF frequency of 45.75 MHz. The
Main VCO Loop will track the incoming IF signal while
maintaining phase and frequency lock as the loops settle.
This is attainable because the tuner AFT loop response is
slow while the Main VCO loop is fast. For large frequency
errors during this period, the slew rate of the tuner LO loop is
automatically increased but not to the extent where it would
cause a VCO tracking problem. This technique allows the
acquisition time of the circuit to be reduced considerably
while still using a larger than normal time constant in the
tuner LO loop. In this way, any possibility of phase
modulating the LO with video is removed.
The amount of AFT offset is controlled by the output swing
of Pin 11, the voltage to frequency sensitivity of the tuner's
AFT input, voltage gain or attenuation of any interface level
shifting circuitry, and the alignment accuracy of the VCO coil.
The amount of VCO offset and VCO sweep is controlled by
the change in capacitance ratio of the internal tuning
capacitance to that of the fixed external tank capacitors C19
and C20. To insure proper PLL lock, it is recommended that
the VCO sweep is limited to less than 5.0 MHz and that C19
and C20 are not be less than 33 pF.
MOTOROLA ANALOG IC DEVICE DATA
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