IC BLOCK
DIAGRAMS
IC701 CXA1782BQ
el IL DATA REGISTER
eiNPUT SHIFT REGISTER
eADRESS. DECODER
*OUTPUT DECODER
su
&
TZC COMP
8
Ly
NAAN
eal:
/\ Togi-3 FSt-4 TGi-2 TWI-7.PS1-4
me
=
os
a
TG1
O
FCS PHASE COMPENSATION
FS
1
O
jot
S
©
OFCT
=
rm
o—O
A
*WINDOW COMP.
Oo
O
:
pg
