Table of Contents
Advertisement
Circuit Diagrams and PWB Layouts
SSB: Interface STI7100
1
1
2
2
A
A
1
B
B
A
C
C
B
D
D
E
E
C
F
F
2AC0
3AC1
470R
D
G
G
PCMOUT2
PCMOUT3
E
PCMOUT4
H
H
1
I
I
J
J
MULTI 12NC : 3139_283_30162
BD 12NC
: 3139_283_30172
1
1
2
2
PB52.3HU LA
10.
3
3
4
4
5
5
6
6
2
3
4
7A00-1
STI7100YWC
Φ
AV
INTERFACE
L34
D34
0
R0OUT
L33
F34
1
VIDANA
G0OUT
K34
E34
2
B0OUT
K33
3
J34
D33
4
IDUMPR0
J33
F33
5
IDUMPG0
VIDANA
H34
E33
6
IDUMPB0
H33
7
U30
A34
8
VIDDIGOUTYC
C1OUT
T31
C34
9
VIDANA
CV1OUT
T30
B34
10
Y1OUT
R31
11
IAC2
R30
A33
12
IDUMPC1
P31
C33
13
VIDANA
IDUMPCV1
P30
B33
14
IDUMPY1
N31
15
A31
REXT0
M34
VIDANA
A32
VSYNC
REXT1
M33
VIDDIGOUT
HSYNC
B31
IAC4
GNDAREXT0
1u0
C28
VIDANA
B32
VBGFIL
GNDAREXT1
C27
AUDANA
IREF
IAC5
IAC3
B28
U33
MRIGHT
TXCP
A28
U34
PRIGHT
TXCN
T33
AUDANAOUT
TX0P
B27
T34
MLEFT
TX0N
A27
R33
PLEFT
TMDS
TX1P
R34
TX1N
D24
P33
SPDIF
TX2P
E24
P34
SCLK
TX2N
E26
AUDOUT
LRCLK
FAC0
D26
T32
PCMCLK
TMDSREF
A25
0
COMPENSATION RESISTOR
B25
D29
1
DATAIN
C25
D28
2
AUDPCMOUT
AUDDIG
DSTRBIN
D25
E28
3
DLRCLKIN
E25
4
2
3
4
3
3
4
4
5
5
6
6
EN 92
8
8
9
9
7
7
5
6
RES
+3V3
+3V3
2AC1
FAC1
7AC0
+3V3
BC847BW
1u0
FAC3
FAC2
3AC8
FAC4
2AC2
FAC5
68R
100n
3AC2
12K
3AC3
22K
3AC4
12K
3AC5
22K
DRXC+
DRXC-
DRX0+
DRX0-
DRX1+
DRX1-
DRX2+
DRX2-
3AC9
+3V3TMDS
100R
3ACC
100R
5
6
CHN
DC398881
SETNAME
CLASS_NO
3PC333
BDS MODULES
-- -- --
1
PCB SB PB522_LN
2009-05-15
2
2009-07-31
3
NAME
YiPing Guo
SUPERS.
SV
CHECK
DATE
7
7
8
8
9
9
2009-Oct-09
10
10
11
11
12
12
7
8
2AC0 D2
2AC1 B6
2AC2 C6
2AC3 C7
3AC1 D1
3AC2 C4
3AC3 C4
3AC4 D4
3AC5 D4
3AC6 B6
3AC7 C6
A
3AC8 C7
3AC9 E4
3ACA C6
3ACB C6
3ACC E4
7A00-1 B3
7AC0 C6
FAC0 E4
FAC1 B6
FAC2 C7
FAC3 C6
FAC4 C6
B
FAC5 C6
IAC1 C7
IAC2 C4
IAC3 D4
IAC4 D2
IAC5 D2
2AC3
IAC1
100n
C
D
E
7
8
3139 283 3017
43
1
0
1
3
0
2009-05-15
ROYAL PHILIPS ELECTRONICS N.V. 2009
C
10
10
11
11
12
12
13
13
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
I
I
2
2009-07-31
2
2009-07-28
J
J
36
A3
13
13
18730_535_090918.eps
090918
Advertisement
Table of Contents
