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By
performing
polarity
and mono/stereo
recognition using
signals
within
this
frequency
band, these recognition
circuits
ignore
low-frequency
disturbances
(like
hum), and
also
ignore high frequencies (which
tend
to
have
interchannei
phase
errors
due
to
time
delays
between
the
left
and
right
channels
of
practical
audio
recorders).
The Auto
Polarity
circuit
compares
the
peak
level of
the
bandpassed
L+R
with the
peak
level of the
bandpassed L-R.
If
the
L-R
exceeds
the
L+R
by
2:1 for a
significant
period,
the
circuit
assumes
that the input
is
"out-of-phase",
and automatically
reverses
the polarity of the
right
channel on
the next zero-crossing.
1)
L+R
Peak
Detector
IC16a, 1C17
form
a
positive
peak
detector
for
L+R.
This circuit
is
capable
of
following
signal
envelopes very
quickly,
yet has
relatively
low
ripple.
The
left
and
right signals are
summed
in
R223, R227.
R223
adds
a
DC
offset to
make
sure that the
peak detector output
is
clamped
to
approximately
+25mV
in
absence
of signal to
avoid
false
operation
of
the polarity detector
on
noise.
The
basic
peak
detector
is
CR201,
C216.
R228
closes a
feedback
loop
around the
peak
detector
to
improve
accuracy.
Every time
that
IC16a
supplies a
charging pulse
to
C216
through
CR201,
it
also
charges
C215
through
CR202.
C215
discharges through
R232. As
long as pulses
occur
more
than every
8ms
or
so,
C215
will
remain
sufficiently
charged
to
keep
the
output
of
IC17a
close to -15V,
which
will
keep
Q201
off.
When
Q201
is
off,
C216
can
only discharge slowly
through R235.
However,
if
a
charging
pulse has not
occurred
for
8ms,
the output of
IC17a goes
high,
and
Q201
turns on,
connecting
R234
in
parallel
with
R235,
thus
speeding
recovery. This switching
between
fast
and slow time constants
allows the
peak
detector
to
follow
falling
envelopes
quickly, yet limits the
amount
of ripple
modulation on
its
output.
2)
L+R/L-R
Comparator
And Time
Constant
The peak-detected
L+R
is
applied
to
the "+" input of IC18, while -(L-R)/2,
derived
in
lC16b,
is
applied
to
lC18's
input.
Unless the peak
level of
-(L-R)/2
exceeds
the
peak
level of the
L+R
at
some
time, the output
of
IC18
will
always be
high
(close to
+15V).
However,
if
the
peak
level
is
exceeded,
IC18's
output
will
go low
(towards -15V) on every peak
which exceeds
the
level,
charging
C217
towards -15V
through
CR204
and R237.
A
few
peaks
will
not be sufficient
to
trip
the
circuit.
However,
consistently
dense
peaks
will
discharge
C217
below
-7.5V,
forcing the
output
of
IC19
HIGH.
This
upward-going
pulse clocks
D
flip-flop
IC14a.
IC14a
is
connected
(through IC14b,
which
delays
transitions
until a
right-channel audio zero-crossing)
to
the polarity
switch
Q101
in
the
right
channel audio
path.
Q101
forces
IClOa
to
be non-inverting
when
IC14a's
output
is
LOW
(ground),
and
to
be
inverting
when
IC14a's
output
is
HIGH
(+15V).
IC14a
is
configured
to
change
state
on every
clock
pulse.
lC14a
therefore corrects the
polarity
by changing state
when
a
clock pulse
is
received.
To
minimize
audible
clicks
when
the
polarity
is
changed,
it
is
desirable to
switch
on
a zero-crossing of the
right
channel
signal.
IC15
is
a zero-crossing detector:
It
6-4
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