3·3 LOGIC CIRCUITS
3·3·4
BAND SELECTION DATA (LOGIC
UNI
The LOGIC circuit consists ol a one
chip
a-bit CPU (ICS),
an 1/0
expander (1C4)
controlling the
input
level l rom
tne
key
matrix,
a
84
k-bit
CMOS RAM (ICll) and a
CI·Y
c
ircuit.
The 64 k·bi\ CM05 RAM (ICll) contains 900 memory
channels which
can ba divided into 9
banks and 20 inde-
pendent. program channels.
The
CI·V
circuit controts
frequency, mode,
memory channels etc..
by
connecling
the rec eiver
with
an
optional
CT·17
CI·Y
LEVEL
CON·
YERTER
to a personal computer
equipped
w
ith
an
RS·232C
port.
3·3·1 RESET CIRCU
IT
(LOGIC UNIT)
The reset circuit
resets
the CPU
(ICS),
the LCD
drivers
(1C8, IC9) and
the
1/0
expander
(1C4) when the
three-
term inal
voltage
regulat o r
(IC13)
detects S
V and outpu ts
S
Y.
The
leading
edge vo ltage is
applied
to a time
con-
stant
(R24,
C22).
The
"
LOW"
pulse-type
signal
is
output
trom
the time
constant
during
Ihe delay time
.
The
signal
Is inverted at 06 and is Ihen applied to a
Schmitl t
rigger c
ircuit (IC7)
to tu
ne
the pulse-type
signaI.
The
rese
t
signal
is
applied
to
the reset
ports
ol
the
CPU
(ICS), the
LCD
dr
ivers
(ICa,
IC9)
and the 1/0
expand er
(1C4).
0
14 discharges
the
voltage
of
C22
.
3·3·2
DIMMER CIRCUIT (LOGIC UNIT)
The
band
control
signaIs
are
changed
depending on
.
receive
trequencies.
The CPU (ICS)
outpu ts
the lollow
signals
for the RF
UNIT,
PLL UNIT and MAIN
UNIT.
RECEIVE
RF
BAN D
PLL
FREQUENCY
CONV
Bl B2
B3
84 BH SS VS
25.0000-
H
L
L
L
L
L
H
L
89.9999
MHz
90.0000-
L
H
L
L
L
L
H
L
249.9999
MHz
250.0000-
L
L
H
L
H
L
L
L
511.9999
MHz
512.0000-
L
L
L
H
L
H
H
L
761
.9999
MHz
762.0000-
L
L
L
H
H
H
L
L
1024.9999 MHz
1025.0000-
H
L
L
L
L
L
H
H
1089.9999
MHz
1090.0000-
L
H
L
L
L
L
H
H
1249.9999
MHz
1250.0000-
L
L
H
L
H
L
L
H
1511.9999
MHz
1512.0000-
L
L
L
H
L
H
H
H
1761
.9999
MHz
1762.0000-
L
L
L
H
H
H
L
H
1999.9999 MHz
Ths dimmer
circuit consists
of
02.
03 and 0
16
and
drives
backlights
(0 54- 0 5 7), ensuring
tnat
brightness does
not
change even
with
a change of
power
supply.
When
tne
[DIM MER]
swi tch is ON, the
CPU (ICS, pin
56)
outputs
a
"
LOW
"
signal
to
decrease
the base
voltage
of
03.
• DIMMER CIRCUIT
3·3·3 REGULATOR CIRCUIT (LOGIC UNIT)
IC23 is a S
Y
th
ree-terminal
reg
ulator.
The "LHV" line
is
converted trom
me
"HV"
line and
passes through a
resistor
(R29l)
on the MAIN
UNIT.
Then,
the voltage
line
is
applied to
IC23.
The time constant
consists
of
R29l
on
the MAIN
UNIT and
C7l
on
the LOGIC UNIT
and protscts
Ihe 5 V line
trom
any
drastic changes.
3·3·S CPU (I CS) PORT ALLOCATJONS
(LOGIC UNIT)
PORT
PORT
PIN
DESCRIPTION
NUIoABER NAME NUIoABER
POO-
B'l -r-
14- 18
Outputs
the
band
control signals
P04
84
, BH
for
the
RF
UNIT.
See
the
table
shown
In
the
BAND SELECTlON
DATA
(3-3-4).
P05
CONV
19
Outputs
a
band
cont
rol signal for
the
MAIN
UNIT.
See the tabla
shown in the BAND
SELECTlON
DATA
(3-3-4).
POS.
VS, SS
20,
21
Outputs
the
band control
signals
,
P07
lor
the
PLL
UNIT.
See the tabla
shown in the BAND
SELECTION
DATA
(3'3-4).
PlO
DIM
56
Becomes ··LOW"
when
the
(DIMMER]
switch
is
ON.
Pl
l
SSTB
57
Outputs
a strobe
signal tor an
optional
UT·36
VOICE
SYNTHESIZER
UNIT.
P12
PSTB
SB
Outputs
a strobe
signal
lor a PLl
IC (IC1
)
on
the
PLL
UNIT.
P13
EXSTB
59
Outputs a
strot>e
signal
lor a
DIA
control
IC
(IC14)
on the
PLL
UNIT.
P14
REML
61
Outputs
an indicator slgnal
tor
Ihs
(AEMOTE]
indicator
on the Ironl
panel.
This
pon
becomes
"HIGH" when the
CPU
enters
1
he
remale
condition via
the
CIN
system.
•
DS'
DS'
FIg.
11
"
.
(
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I)
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RU
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f
,
•
e
•
•
•
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••
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Ru
r
'J.
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...
,
...
UC3l
..
DO
3 -
12
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