Table of Contents
Advertisement
=] —> ela 4
@ Frequency Synthesizer Section (MW)
The
MW
section
employes a direct
frequency
dividing
ehenne rn
nae Tuner
Hees
method. So that the reception frequency is incremented in
9 kHz, the frequency of the phase comparator
is 9 kHz.
This is produced by dividing 4.5 MHz (the output of X2),
a clock
frequency
of IC7, to 1/500. Since the reception
frequency
range is 531 ~ 1,602 kHz and the intermediate
frequency
is selected at 450 kHz, the frequency of the local
oscillator (VCO) will be 981 ~ 2,052 kHz.
wT orace
This output
is output from pin 12 of
IC5
and enters pin
Loop Filter
0
9 of IC7.
x2
If the frequency dividing ratio of the.programmable counter
in IC7 is set to 109 ~ 228, the output will be 9 kHz. This
frequency
is compared
in phase with a reference frequency
of 9 kHz by the phase comparator and is output from pin
12 of IC7.
The signal is converted into a DC voltage signal by the loop
filter consisting of Q22
and
Q23, which in turn controls
the tuning circuit as a tuning voltage.
@ The Functions of Control IC (PD4052A)
PD4052A is a 52-pin flat package C-MOS LSI which controls
25kHz incremental tuning for FM, 9kHz incremental tuning
for AM. This PLL type frequency synthesizer tuner control IC
makes
possible
7-segment
digital
display.
Since
this
IC
employs
a static method
for the display driver, the per-
formance of the receiver is improved.
KEY BOARD
MUT ING
CIRCUIT
Fig. 16
11
Advertisement
Table of Contents
