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9H-4-45.
Referring again to Figure 9H-4-6, assume
that U7D pin 8 is High. After reset and before the first
: Channel B input pulse, the initial conditions are as
follows: U11A(12) is High, since both inputs are Low;
U20B(6) is Low, since both inputs are High. When thein-
put signal goes Low, U7C(4) goes High, U7D(8) goes
Low, U20B(6) goes High and clocks the AGFF. When the
flip-flop toggles, it removes the Low on U11A(1,2) and
results in a Low on U20B(4). Since both inputs are Low,
the output of U20B also goes Low. This enables U20B to
respond to the stop portion of the input pulse. When the
input signal returns High, U7D(8) returns High and
U20B clocks the AGFF close, ending the measurement.
9H-4-46.
TIME INTERVAL AVERAGE
A TO B MODE
9H-4-47.
The number of time intervals to be averaged
is determined by the TIME BASE switch setting, e.g.,
103, 10%, 105, etc. time intervals.
During
each time
interval, the mainframe's Time Base Decades record the
number
of time intervals by counting
synchronized
Channel A pulses. When the counter accumulates the
proper
number
of
intervals,
it
terminates
the
measurement
with a LOG pulse. Refer to the Time
Interval Average Flow Diagram, Figure 9H-4-7 for the
following descriptions.
9H-4-48.
The
"time zero" LOG
pulse enables
the
counter to make a measurement by clocking the AGFF
(U17A). This places a High on U8B(2) and allows the
gate to pass clock pulses during each individual time
interval. After the Channel A pulse sets flip-flop U6C
and D, the next 10 MHz clock pulse sets U9B, which
enables U14A to pass the 10 MHz clock signal. The
signal accumulates counts in the High Speed Decade
and in the mainframe's counter until the Channel B
pulse ends the time interval, It does this by setting U6A
and B, allowing the next clock pulse to set U9A. The
High on the Q output disables U14A from passing the
clock pulses.
Model 5308A
Theory of Operation
9H-4-49.
The counter continues accumulating clock
pulses during the time A to B until 104
time intervals
have been measured. At this point, the TB OUT line goes
Low and clocks U17B via Q6, U16C, U12A, and U12D.
When U17B sets, it places a low level on the D input of
U17A. The following LOG pulse clocks U17A. This ends
the measurement by disabling U8B.
9H-4-50.
TIME INTERVAL A TO B MODE
9H-4-51.
A single time interval is measured by open-
ing the gate with the Channel A signal and counting the
10 MHz clock signal (or 10 MHz/ 10N) untilthe Channel
B signal closes the gate. Refer to Time A — D Mode Flow
Diagram, Figure 9H-4-8.
9H-4-52.
When Channel A triggers, it sends a positive
pulse to differentiator C30 and R63. The resulting spike
sets flip-flop
U6C and D and places a High on U9B(12).
On the next positive-going edge of the clock signal, the Q
output goes Low and enables U14C.
9H-4-53.
Prior to the Channel A trigger pulse, U20B
pin 4 was High, due to the inputs of ULIA being Low;
and U20B(5) was High, since U7A(1) was Low. These
conditions caused U20B(6) to sit at a Low level. Once
U14C(8)
goes
High, it removes
the High
level at
U7D(8)
and
allows
U20B
to clock the AGFF.
The
resultant High on the Q output causes U20B pins 4
and 6 to go Low. U8B and D pass the divided clock
signal to the High Speed
Decade
and then to the
mainframe. The Low on U17A(6) is inverted by U12C
and U12D
to clock U17B. The resultant Low on Q
enables U17A to close at a later time.
9H-4-54,
Once the Channel B pulse arrives, it sets
flip-flop U6A and B, causing a High on the D input
of USA. The next clock pulse disabies U14C by plac-
ing a High on pins 9 and 10. This disables U14C and
allows U7D(8) to go High and close the AGFF
through
U20B. The Low on the Q output of U9A enables U14B
to pass the 10 MHz
clock to the reset lines of U9A
and B.
9H-4-5
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