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SSC-C104/C108P
CXD1267AN
(SONY) FLAT PACKAGE
CMOS
VERTICAL
CLOCK
DRIVER
FOR CCD
- TOP VIEW —
|
sane
; OPERATIONAL AMPLIFIRE INPUT
8)
O—~~)
XSG1. XSG2: SENSOR GATE PULSE INPUT
—e
@
zzZ22
2
3
XSHT
; SAMPLE AND HOLD PULSE INPUT
Zz
2
p22
=
=
XV1~XV4_;
VERTICAL REGISTER TRANSMISSION CLOCK INPUT
aan
a
8
OUTPUT
CPP3
; CHARGE PUMP
pcouT
: OPERATIONAL AMPLIFIRE OUTPUT
VSHT
; SAMPLE AND HOLD PULSE OUTPUT
VO1-V04
; VERTICAL REGISTER TRANSMISSION CLOCK OUTPUT
CXD2401R (SONY)
ELECTRONIC IRIS CONTROL IC
INPUT
—TOP VIEW—
CK
;CLOCK
ENB
sELECTRONIC SHUTTER PULSE GENERATION/STOP SWITCH
CONTROL
HD
sHORIZONTAL SYNCHRONIZING SIGNAL
IRENB = ;ELECTRONIC IRIS/SHUTTER SWITCH CONTROL
IRIN
{ELECTRONIC IRIS MODE: IRIS SIGNAL ~
ELECTRONIC SHUTTER-SERIAL MODE: CLOCK
LIMIT1,2 ;SHUTTER SPEED LIMIT VALUE SELECT
NTSC
;NTSC/PAL SWITCH CONTROL
OSCI
= OSCILLATION INVERTER
PS
;ELECTRONIC SHUTTER SPEED DATA PARALLEL/SERIAL SWITCH
.
CONTROL
SPDNV_
ELECTRONIC IRIS MODE: SHUTTER SPEED DOWN REFERENCE
VOLTAGE
ELECTRONIC SHUTTER SERIAL MODE: DATA
SPUPV
;ELECTRONIC IRIS MODE: SHUTTER SPEED UP REFERENCE VOLTAGE
ELECTRONIC SHUTTER SERIAL MODE: STROBE
eo lal oe Be Bo
O8cl
fof te ___/asio| wisi
=| exo —_
zo osco
[rato
las) o |
xsar—|s0]
| seurv |
fafitic«
tislol cure
ferfoT xa
foot tT ai
ose
|
CLP1,2,4 ;CLAMP PULSE
H1,2
;CCD HORIZONTAL CLOCK
ID
;LINE DETECT
OSCO_
;OSCILLATION INVERTER
PaE#i
AT ee Ce
Ce
el
PBLK
BLANKING
CLEANING
PULSE
fete) xe
Jaslo tvs
sae
l=[ee fae ee fete
sien
gett arah Sicd brik data
XDL1,2 ;CLOCK (DELAY LINE)
XSG1,2 ;CLOCK (CCD SENSOR READ OUT)
XSHD
SAMPLE/HOLD PULSE (DATA LEVEL)
XSHP
'SAMPLE/HOLD PULSE (PRE-CHARGE LEVEL)
XSP1,2 ;SAMPLE/HOLD PULSE
XSUB
;CLOCK (CCD ELECTRON SHUTTER)
XV1,2,3,4
;CCD VERTICAL CLOCK
Sete
et
=|
voo
[ xse2_jaslo|
xe
[as{ 1 [| ps
wolo{
cues
fzzto| xmr
__fas[oj re
[4g] 1 | unars
[nfoj cups
jasfo| xo2 _ [ast-| voo
fait | ume
lol peux
[2s|
[ssiv tom
last
ntsc |
5-23
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